5027720063

Course: Computer Science | Leyel: graduate
Subject: Digital ASIC design in submicron TECHNOLOGIES	DURATION - LECTURES: 15H LAB. EXC.: 15H
System: Full-time | Year: 5	Semester: 9
Lecturer: dr Robert Szczygieł, dr hab. Paweł Gryboś (Faculty of Physics and Applied Computer Science)

Aims

The aim of the course is introduction of the digital VLSI ASIC design methodology based on state-of-the-art submicron technologies.

Topics

1.    Introduction into digital ASIC design.

2.    Standard celi libraries

3.    Timing issues, design constraints.

4.    Verilog HDL, functional simulations.

5.    Synthesis, Verilog modeling for synthesis

6.    Layout generation: placement, power planning, clock tree generation, routing etc.

7.    Static timing analysis and finał verification

Objectives

Combinational and seąuential logie modeling in Verilog HDL, for synthesis. Timing constraints definitions for synthesis. Synthesis of digital ASIC's. ASIC layout generation.