plik


ÿþI T P W ZPT 1 Realizacja PLA a y1 = abc + ac + b c b y2 = ac + b c + ad c d a b y1 c y1 y2 d I y2 T P W ZPT 2 Realizacja PAL y1 = abc + ac + b c y2 = ac + b c + ad a b c d I y1 T P W y2 ZPT 3 Matryce PLA - powierzchnia krzemu P x1 x2 2 n AND xn f0 f1 m OR fm-1 I T P S = (2n + m) P * W ZPT 4 UkBady wielowyj[ciowe - przykBad y1 = £(2,3,5,7,8,9,10,11,13,15) y1 = ab + bd + bc y2 = £(2,3,5,6,7,10,11,14,15) y3 = £(6,7,8,9,13,14,15) y2=c+abd a a a b b y3 =bc+acd+abc b c c d d c d y1 y1 y2 y2 Powierzchnia matrycy: y3 y3 S = (2Å" Å"P Å"n + m)Å" Å"Å" Å"Å" I S = (2Å" Å"8 = 88 Å"4 + 3)Å" Å"Å" Å"Å" T P W ZPT 5 UkBady wielowyj[ciowe - przykBad y1 = £(2,3,5,8,9,10,11,13,15), +abc y =bc +abd +abd 1 y2 = £(2,3,5,6,7,10,11,14,15) y3 = £(6,7,8,9,13,14,15) +bc y =bc +abd 2 y3 = abd +abc +bc 1 2 3 4 5 a b c d y1 y1 y2 y2 y3 y3 S = (2Å" Å"Å" Å"4 + 3)Å" I Å"Å" Å"5 = 55 T P W ZPT 6 UkBady programowalne& CPLD FPGA I T P charakteryzuj si ziarnist budow W ZPT 7 Struktury programowalne MAX I/O OUTPUT ENABLE SYSTEM CLOCK PRESET P D Q TO I/O ARRAY CLOCK CONTROL C BLOCK CLEAR From From Expander I/O and inputs PIA Product Macrocell Terms Feedback 8 macro cell AND 8 macro Array cell I T 8 macro P cell W PLD ZPT 8 UkBady FPGA firmy Xilinx Configurable Logic blocks (CLBs) .di DATA IN 0 MUX D Q F DIN 1 G RD QX .X QX .a F F .b LOGI C CLB .c CO MBINATIONAL VARIABLES .d FUNCTION OUTPUTS .e G G .Y QY QY F 0 DIN G MUX D Q 1 RD .ec ENABLE clk "1" (ENABLE) .k clk .rd RESET "0" (I NH IBIT) I (GLOBAL RESET) T P W ZPT 9

Wyszukiwarka

Podobne podstrony:
121010141958?c english at work episode6
the strike at shayol ghul
new?atures 1 1
120702094621 english at work episode! final
AT praca zal PBG
Hotel at The end of The Road
120829102127?c english at work episode) en
Prim to be good at
H P Lovecraft At the Root
Mobb?ep Where ya Heart at
Kurs AT lekcja1
CoC The Horror at Red Hook
HG551V PS AT

więcej podobnych podstron