usage statistics webtalk


Device Usage Statistics Report

Device Usage Page (usage_statistics_webtalk.html)This HTML page displays the device usage statistics that will be sent to Xilinx.  

Software Version and Target Device

Product Version:
ISE:13.3 (WebPack) - O.76xd
Target Family:
Spartan3A and Spartan3AN


OS Platform:
NT64
Target Device:
xc3s700a


Project ID (random number)
432acfb726f04b43b5ca636b6cea6e33.50F717AD76EA40B1AD49FEDFC5F9BA2E.1
Target Package:
fg484


Registration ID
211190159_0_0_559
Target Speed:
-4


Date Generated
2016-05-18T19:35:00
Tool Flow
ISE


 

User Environment

OS Name
Microsoft Windows 7 , 64-bit
OS Release
Service Pack 1 (build 7601)


CPU Name
Intel(R) Core(TM) i7-3610QM CPU @ 2.30GHz
CPU Speed
2294 MHz


 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage


Adders/Subtractors=5

4-bit addsub=5


Comparators=6

20-bit comparator greatequal=1
20-bit comparator less=1
21-bit comparator greatequal=1
21-bit comparator greater=1
21-bit comparator lessequal=2


Counters=3

20-bit up counter=1
21-bit up counter=1
6-bit up counter=1


FSMs=3

Registers=87

Flip-Flops=87






MiscellaneousStatistics

AGG_BONDED_IO=16
AGG_IO=16
AGG_SLICE=258
NUM_4_INPUT_LUT=400
NUM_BONDED_IBUF=5
NUM_BONDED_IOB=11
NUM_BUFGMUX=3
NUM_CYMUX=106
NUM_DCM=1
NUM_LUT_RT=46
NUM_SLICEL=258
NUM_SLICE_FF=194
NUM_XOR=41
Xilinx Core dist_mem_gen_v6_2, Xilinx CORE Generator 13.3=1




NetStatistics

NumNets_Active=504
NumNets_Gnd=1
NumNets_Vcc=1
NumNodesOfType_Active_CLKPIN=127
NumNodesOfType_Active_CNTRLPIN=167
NumNodesOfType_Active_DOUBLE=983
NumNodesOfType_Active_DUMMY=1273
NumNodesOfType_Active_DUMMYBANK=3
NumNodesOfType_Active_DUMMYESC=6
NumNodesOfType_Active_GLOBAL=54
NumNodesOfType_Active_HFULLHEX=9
NumNodesOfType_Active_HLONG=1
NumNodesOfType_Active_HUNIHEX=52
NumNodesOfType_Active_INPUT=1450
NumNodesOfType_Active_IOBOUTPUT=5
NumNodesOfType_Active_OMUX=537
NumNodesOfType_Active_OUTPUT=486
NumNodesOfType_Active_PREBXBY=424
NumNodesOfType_Active_VFULLHEX=51
NumNodesOfType_Active_VLONG=15
NumNodesOfType_Active_VUNIHEX=67
NumNodesOfType_Vcc_CNTRLPIN=3
NumNodesOfType_Vcc_INPUT=5
NumNodesOfType_Vcc_PREBXBY=5
NumNodesOfType_Vcc_VCCOUT=7


SiteStatistics

IBUF-DIFFSTB=2
IOB-DIFFMTB=5
IOB-DIFFSTB=6
SLICEL-SLICEM=101






SiteSummary

BUFGMUX=3
BUFGMUX_GCLKMUX=3
BUFGMUX_GCLK_BUFFER=3
DCM=1
DCM_DCM=1
IBUF=5
IBUF_DELAY_ADJ_BBOX=5
IBUF_INBUF=5
IBUF_PAD=5
IOB=11
IOB_OUTBUF=11
IOB_PAD=11
SLICEL=258
SLICEL_C1VDD=23
SLICEL_C2VDD=23
SLICEL_CYMUXF=56
SLICEL_CYMUXG=50
SLICEL_F=205
SLICEL_F5MUX=20
SLICEL_F6MUX=5
SLICEL_FFX=101
SLICEL_FFY=93
SLICEL_G=195
SLICEL_GNDF=33
SLICEL_GNDG=27
SLICEL_XORF=21
SLICEL_XORG=20





 
Configuration Data


BUFGMUX

S=[S_INV:3] [S:0]


BUFGMUX_GCLKMUX

DISABLE_ATTR=[LOW:3]
S=[S_INV:3] [S:0]


DCM

PSCLK=[PSCLK_INV:0] [PSCLK:1]
PSEN=[PSEN_INV:0] [PSEN:1]
PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
RST=[RST:1] [RST_INV:0]


DCM_DCM

CLKDV_DIVIDE=[2:1]
CLKOUT_PHASE_SHIFT=[NONE:1]
CLK_FEEDBACK=[1X:1]
DESKEW_ADJUST=[8:1]
DFS_FREQUENCY_MODE=[LOW:1]
DLL_FREQUENCY_MODE=[LOW:1]
DUTY_CYCLE_CORRECTION=[TRUE:1]
FACTORY_JF1=[0XC0:1]
FACTORY_JF2=[0X80:1]
PSCLK=[PSCLK_INV:0] [PSCLK:1]
PSEN=[PSEN_INV:0] [PSEN:1]
PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
RST=[RST:1] [RST_INV:0]
STARTUP_WAIT=[STARTUP_WAIT:1]




IBUF_DELAY_ADJ_BBOX

DELAY_ADJ_ATTRBOX=[FIXED:5]
IBUF_DELAY_VALUE=[DLY0:5]
IFD_DELAY_VALUE=[DLY0:5]
SEL_IN=[SEL_IN:5] [SEL_IN_INV:0]


IBUF_PAD

IOATTRBOX=[LVCMOS25:5]


IOB

O1=[O1_INV:0] [O1:11]


IOB_OUTBUF

IN=[IN_INV:0] [IN:11]
SUSPEND=[3STATE:11]


IOB_PAD

DRIVEATTRBOX=[12:11]
IOATTRBOX=[LVCMOS25:11]
SLEW=[SLOW:11]


SLICEL

BX=[BX_INV:1] [BX:72]
BY=[BY:59] [BY_INV:0]
CE=[CE:61] [CE_INV:0]
CIN=[CIN_INV:0] [CIN:47]
CLK=[CLK:125] [CLK_INV:0]
SR=[SR:105] [SR_INV:0]




SLICEL_CYMUXF

0=[0:56] [0_INV:0]
1=[1_INV:0] [1:56]


SLICEL_CYMUXG

0=[0:50] [0_INV:0]


SLICEL_F5MUX

S0=[S0:20] [S0_INV:0]


SLICEL_F6MUX

S0=[S0:5] [S0_INV:0]


SLICEL_FFX

CE=[CE:52] [CE_INV:0]
CK=[CK:101] [CK_INV:0]
D=[D:100] [D_INV:1]
FFX_INIT_ATTR=[INIT0:96] [INIT1:5]
FFX_SR_ATTR=[SRLOW:96] [SRHIGH:5]
LATCH_OR_FF=[FF:101]
SR=[SR:87] [SR_INV:0]
SYNC_ATTR=[ASYNC:41] [SYNC:60]


SLICEL_FFY

CE=[CE:41] [CE_INV:0]
CK=[CK:93] [CK_INV:0]
D=[D:93] [D_INV:0]
FFY_INIT_ATTR=[INIT0:90] [INIT1:3]
FFY_SR_ATTR=[SRLOW:90] [SRHIGH:3]
LATCH_OR_FF=[FF:93]
REV=[REV_INV:0] [REV:1]
SR=[SR:74] [SR_INV:0]
SYNC_ATTR=[ASYNC:32] [SYNC:61]




SLICEL_XORF

1=[1_INV:0] [1:21]





 
Pin Data


BUFGMUX

I0=3
O=3
S=3


BUFGMUX_GCLKMUX

I0=3
OUT=3
S=3


BUFGMUX_GCLK_BUFFER

IN=3
OUT=3


DCM

CLK0=1
CLKFB=1
CLKFX=1
CLKIN=1
LOCKED=1
PSCLK=1
PSEN=1
PSINCDEC=1
RST=1
STATUS2=1


DCM_DCM

CLK0=1
CLKFB=1
CLKFX=1
CLKIN=1
LOCKED=1
PSCLK=1
PSEN=1
PSINCDEC=1
RST=1
STATUS2=1




IBUF

I=5
PAD=5


IBUF_DELAY_ADJ_BBOX

IBUF_OUT=5
SEL_IN=5


IBUF_INBUF

IN=5
OUT=5


IBUF_PAD

PAD=5


IOB

O1=11
PAD=11


IOB_OUTBUF

IN=11
OUT=11


IOB_PAD

PAD=11


SLICEL

BX=73
BY=59
CE=61
CIN=47
CLK=125
COUT=50
F1=204
F2=175
F3=150
F4=117
F5=10
FXINA=5
FXINB=5
G1=195
G2=164
G3=150
G4=110
SR=105
X=107
XB=5
XQ=101
Y=110
YQ=93




SLICEL_C1VDD

1=23


SLICEL_C2VDD

1=23


SLICEL_CYMUXF

0=56
1=56
OUT=56
S0=56


SLICEL_CYMUXG

0=50
1=50
OUT=50
S0=50


SLICEL_F

A1=204
A2=175
A3=150
A4=117
D=205


SLICEL_F5MUX

F=16
G=20
OUT=20
S0=20


SLICEL_F6MUX

0=5
1=5
OUT=5
S0=5


SLICEL_FFX

CE=52
CK=101
D=101
Q=101
SR=87




SLICEL_FFY

CE=41
CK=93
D=93
Q=93
REV=1
SR=74


SLICEL_G

A1=195
A2=164
A3=150
A4=110
D=195


SLICEL_GNDF

0=33


SLICEL_GNDG

0=27


SLICEL_XORF

0=21
1=21
O=21


SLICEL_XORG

0=20
1=20
O=20





 
Tool Usage
Command Line History
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
xst -intstyle ise -ifn <ise_file>
ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s700a-fg484-4 <fname>.ngc <fname>.ngd
ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -uc <fname>.ucf -p xc3s700a-fg484-4 <fname>.ngc <fname>.ngd
map -intstyle ise -p xc3s700a-fg484-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
bitgen -intstyle ise -f <fname>.ut <fname>.ncd
fuse


 Software QualityRun StatisticsProgram NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps


arwz
3
3
0
0
0
0
0


bitgen
1
1
0
0
0
0
0


map
1
1
0
0
0
0
0


ngc2edif
4
4
0
0
0
0
0


ngcbuild
2
2
0
0
0
0
0


ngdbuild
2
2
0
0
0
0
0


par
1
1
0
0
0
0
0


trce
2
2
0
0
0
0
0


xst
7
7
0
0
0
0
0



 

Project Statistics

PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTML

PROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked)

PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all values

PROP_SelectedInstanceHierarchicalPath=/stopwatch_tb
PROP_Simulator=ISim (VHDL/Verilog)

PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL

PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor

PROP_intProjectCreationTimestamp=2016-04-06T21:25:40
PROP_intWbtProjectID=50F717AD76EA40B1AD49FEDFC5F9BA2E

PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same

PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed

PROP_selectedSimRootSourceNode_behav=work.stopwatch_tb
PROP_xstNetlistHierarchy=Rebuilt

PROP_AutoTop=true
PROP_DevFamily=Spartan3A and Spartan3AN

PROP_DevDevice=xc3s700a
PROP_DevFamilyPMName=spartan3a

PROP_ISimSimulationRunTime_behav_tb=2000 ns
PROP_DevPackage=fg484

PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4

PROP_PreferredLanguage=Verilog
FILE_COREGEN=1

FILE_UCF=1
FILE_VERILOG=7

FILE_XAW=1

 

Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=3
NGDBUILD_NUM_DCM_SP=1
NGDBUILD_NUM_FD=33
NGDBUILD_NUM_FDC=13


NGDBUILD_NUM_FDCE=26
NGDBUILD_NUM_FDP=1
NGDBUILD_NUM_FDR=47
NGDBUILD_NUM_FDRE=66


NGDBUILD_NUM_FDRS=1
NGDBUILD_NUM_FDS=6
NGDBUILD_NUM_FDSE=1
NGDBUILD_NUM_GND=6


NGDBUILD_NUM_IBUF=4
NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=15
NGDBUILD_NUM_LUT1=46


NGDBUILD_NUM_LUT2=44
NGDBUILD_NUM_LUT2_D=1
NGDBUILD_NUM_LUT2_L=1
NGDBUILD_NUM_LUT3=65


NGDBUILD_NUM_LUT3_L=7
NGDBUILD_NUM_LUT4=202
NGDBUILD_NUM_LUT4_D=16
NGDBUILD_NUM_LUT4_L=9


NGDBUILD_NUM_MUXCY=106
NGDBUILD_NUM_MUXF5=16
NGDBUILD_NUM_MUXF6=5
NGDBUILD_NUM_OBUF=11


NGDBUILD_NUM_VCC=2
NGDBUILD_NUM_XORCY=41
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=3
NGDBUILD_NUM_DCM_SP=1
NGDBUILD_NUM_FD=33
NGDBUILD_NUM_FDC=13


NGDBUILD_NUM_FDCE=26
NGDBUILD_NUM_FDP=1
NGDBUILD_NUM_FDR=47
NGDBUILD_NUM_FDRE=66


NGDBUILD_NUM_FDRS=1
NGDBUILD_NUM_FDS=6
NGDBUILD_NUM_FDSE=1
NGDBUILD_NUM_GND=6


NGDBUILD_NUM_IBUF=4
NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=15
NGDBUILD_NUM_LUT1=46


NGDBUILD_NUM_LUT2=44
NGDBUILD_NUM_LUT2_D=1
NGDBUILD_NUM_LUT2_L=1
NGDBUILD_NUM_LUT3=65


NGDBUILD_NUM_LUT3_L=7
NGDBUILD_NUM_LUT4=202
NGDBUILD_NUM_LUT4_D=16
NGDBUILD_NUM_LUT4_L=9


NGDBUILD_NUM_MUXCY=106
NGDBUILD_NUM_MUXF5=16
NGDBUILD_NUM_MUXF6=5
NGDBUILD_NUM_OBUF=11


NGDBUILD_NUM_TS_TIMESPEC=1
NGDBUILD_NUM_VCC=2
NGDBUILD_NUM_XORCY=41

 

XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj
-ifmt=mixed
-ofn=<design_top>
-ofmt=NGC


-p=xc3s700a-4-fg484
-top=<design_top>
-opt_mode=Speed
-opt_level=1


-iuc=NO
-keep_hierarchy=No
-netlist_hierarchy=Rebuilt
-rtlview=Yes


-glob_opt=AllClockNets
-read_cores=YES
-sd=<No customer specific name>
-write_timing_constraints=NO


-cross_clock_analysis=NO
-bus_delimiter=
-slice_utilization_ratio=100
-bram_utilization_ratio=100


-verilog2001=YES
-fsm_extract=YES
-fsm_encoding=Auto
-safe_implementation=No


-fsm_style=LUT
-ram_extract=Yes
-ram_style=Auto
-rom_extract=Yes


-shreg_extract=YES
-rom_style=Auto
-auto_bram_packing=NO
-resource_sharing=YES


-async_to_sync=NO
-mult_style=Auto
-iobuf=YES
-max_fanout=500


-bufg=24
-register_duplication=YES
-register_balancing=No
-optimize_primitives=NO


-use_clock_enable=Yes
-use_sync_set=Yes
-use_sync_reset=Yes
-iob=Auto


-equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5

 ISim StatisticsXilinx HDL Libraries Used=xilinxcorelib_ver, unisims_verFuse Resource Usage=748 ms, 34828 KBTotal Signals=191Total Nets=470Total Blocks=23Total Processes=235Total Simulation Time=2 usSimulation Resource Usage=0.702005 sec, 480284 KBSimulation Mode=guiHardware CoSim=0


Wyszukiwarka

Podobne podstrony:
usage statistics webtalk
usage statistics webtalk
usage statistics webtalk
usage statistics webtalk
device usage statistics
par usage statistics
DBR Instrukcja instalacji STATISTICA wersja jednostanowiskowa 10 PL
printing usage howto 7 2c2zlyaxp24rdykygurm3fzpf23zdirunbridyq
printing usage howto pl 5
script usage example
20 New Techn Statistics etc
Elementary Statistics 10e TriolaE S Creditspp855 856
Redemittel zur Beschreibung von Schaubildern, Diagrammen und Statistiken
elements of statistical learning sol2
Printing Usage HOWTO pl

więcej podobnych podstron