4656880269

Parameterize - FIR Compiler

Coeflicients Specification - (f8 fir (1))

Ratę Specification

New Coefficient Set

Edit Coefficient Set

Remove Coefficient Set

Single Ratę

Factor \2

f8fir [1]

□ Add global dock enable pin

Input Specification

Plot Option

FixecJ/Floating Coefficients ^v □ park Backgrpunęl

Number of Input Channels

Input Number System

Signed Binary

Input Bit Width

8

^v

Output Specification

Fuli Resolution Bit Width is 20 Based on Method

Actual Coefficients v

Output Number System Fuli Resolution

^v

Architecture Specification Device Family

Structure Pipeline Level Data Storage

Cyclone II

Distributed Arithmetic : Fully Parallel Filter

1

Logic Cells	V
Logic Cells

Multlplłer Implementation Logic Cells

Force Non-Symmetric Structure

Coefficients Reload Use Single Clock

Resource	Utilization estimate
Logic Cells	668
M512	0
M4K	0
W-RAM	0
M9K	0
M20K	0
M144K	0
MLA8	0
Multipliers	0

Throughput (Fully Streaming)

• An input data is processed every1 clock periods.

- A new output data is generated every clock period.

I    /^AA^r.AiArtłA t-rtlAAi-J irt AAaWIa/J AaLui (l\AA AAA^AlAA* A*A»AAA i A AAł *A A UIaaI/

ftWA Wt Art •

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