5196106181

CC ML —

new logie Circuit family deue/oped in Australia

A new Australian-developed logie Circuit family could have the potential to give new directions to the Computer industry throughout the world, even while the giants like IBM and Fujitsu have been investing hundreds of millions of dollars in computer-related R&D every year.

by PAUL GRAD

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Mark Silver (left) and Chris Horwitz, developers of the new logie family, discuss a point in their lab at the Unlversity of NSW.

ELECTRONICS Australia. Seotember 1987

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It could also be another case of an important Australian brain-child which is commercialised only overseas, with Australia paying for imports of equip-ment based on a local idea. Manufactur-ing the new circuits would involve set-ting up an entirely new plant requiring an initial investment of about S50 mil-lion and the required R&D would, as with the large manufacturers, cost hundreds of millions of dollars.

It was therefore understandable that there was some surprise when Dr Chris Horwitz of the University of NSW*s school of electrical engineering and Computer science proposed the new logie during the 1987 International VLSI Circuits Symposium in Japan, last May. Horwitz, who went to Japan at the invitation of the symposium organis-ers, had previously attracted attention with his invention about two years ago of a plasma etcher for chip manufac-ture, which is now being commercialised in Australia.

He claims the new logie, called Com-plementary Current Mirror Logic (CCML), which he developed in co-operation with the school’s professional officer Mark Silver, has the potential to allow combining the high speed of operation of bipolar chips with the

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large-scale integration of MOS chips.

It would thus make it possible for PCs to operate with the speed of exist-ing mainframe computers.

Although several types of logie Circuit are currently used, they are all based on variants of two kinds of active compo-nents, bipolar and field-effect transis-tors.

Their fabrication processes are simi-larly based on two technologies, bipolar and MOS.

Bipolar chips are faster than MOS chips, but dissipate morę power. The higher power dissipated by bipolar chips limits the level of integration achievabje with them.

A far higher level of integration is achievable with MOS chips, which are therefore used where smali size of equipment is wanted and where operat-ing speed is not paramount.

Dr Horwitz says that attempts at reducing the power dissipation of bipolar chips led to two main developments. One of them was the refinement of bipolar processing technology, which has permitted Iow gate operating cur-rents with self-aligned PNP and NPN transistor constructions. The other was the improvement in high-speed bipolar gate designs from emitter-coupled logie (ECL), operating with a voltage swing of 5(X)mV, to non-threshold logie (NTL) and current-mode logie (CML) using a voltage swing of 3(K)mV.

These Iow voltage swings have in-creased the speed of bipolar chip operation even further and have also lowered their power dissipation, due to the short time and the Iow energy required to charge gate inputs and interconnections.

However, the continuous current drain of bipolar gates still prevents their integration \o the levels possible with complementary MOS (CMOS), which only draws power w'hen signals change.

Several ideas have been advanced to lower the standing current in bipolar circuitsr, including using complementary