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Functional Design

If the IP performs the required funclion, but does not liave quite the right interface connections or timing, we might be able to embed it in

If the IP has almost the required function and the source codę is available to us, we might be able to make minor changes to adapt its functionality to our needs

Alternative for implementing a component may be to use a core generator

Functional Verification

Verifying each subsystem can be considered to be a prerequisite for verifying the entire system

Components can then be integrated into the next-level subsystem, which is then yerified. The process is repeated. up to the top level of the system.

At higher levels of the design hierarchy, the functionality of subsystems and the complete system gets much morę complex.

Functional Verification

• There are a number of techniques that we can apply

• directed testing: in»olves kfentifying particular test cases to apply to the DUV and checking the output for each test case:

• format yerification: allows complete werification that a component

expressed in a property specihcation language (PSL)). SystemVerilog exten$k>n of Verik>g Includes features similar to those of PSL for expressing properties.