Synthesis Log
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Function IID_IDispatch
IID_IDispatch = "{00020400-0000-0000-C000-000000000046}"
End Function
Function CLSID_Executor
CLSID_Executor = "Aldec.ExePlugIn.Generic.7"
End Function
Sub OpenPlugIn (progid, template, document, element, string)
Dim executor, command
Set executor = window.external.aldec.connector.OpenPlugIn(CLSID_Executor, IID_IDispatch)
command = "?Activate[][][][][]"
executor.ExecuteCommand command, ""
End Sub
Synthesis Log
Created on 12:13:35 12/13/15
Running XST Synthesis...
Please wait...
Release 6.3i - xst G.35
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.42 s | Elapsed : 0.00 / 0.00 s
--> Parameter xsthdpdir set to e:/projekty_vhdl/miroslawcz_proj/miroslawcz_proj/synthesis/xst
CPU : 0.00 / 0.42 s | Elapsed : 0.00 / 0.00 s
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) HDL Analysis
4) HDL Synthesis
5) Advanced HDL Synthesis
5.1) HDL Synthesis Report
6) Low Level Synthesis
7) Final Report
7.1) Device utilization summary
7.2) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : calyuklad.prj
Input Format : mixed
Ignore Synthesis Constraint File : no
---- Target Parameters
Output File Name : calyuklad
Output Format : NGC
Target Device : xcv50bg256-6
---- Source Options
Top Module Name : calyuklad
Automatic FSM Extraction : yes
FSM Encoding Algorithm : Auto
Resource Sharing : yes
FSM Style : lut
RAM Extraction : yes
RAM Style : auto
ROM Extraction : yes
ROM Style : auto
Mux Extraction : yes
Mux Style : auto
Decoder Extraction : yes
Priority Encoder Extraction : yes
Shift Register Extraction : yes
Logical Shifter Extraction : yes
XOR Collapsing : yes
Multiplier Style : lut
Automatic Register Balancing : no
---- Target Options
Add IO Buffers : yes
Global Maximum Fanout : 100
Add Generic Clock Buffer(BUFG) : 4
Register Duplication : yes
Equivalent register Removal : yes
Pack IO Registers into IOBs : auto
Slice Packing : yes
---- General Options
Optimization Goal : speed
Optimization Effort : 1
Global Optimization : allclocknets
RTL Output : yes
Write Timing Constraints : no
Keep Hierarchy : no
Hierarchy Separator : _
Bus Delimiter : <>
Case Specifier : maintain
Slice Utilization Ratio : 100
Slice Utilization Ratio Delta : 5
---- Other Options
verilog2001 : yes
cross_clock_analysis : no
Read Cores : yes
tristate2logic : yes
Optimize Instantiated Primitives : no
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file e:/projekty_vhdl/miroslawcz_proj/miroslawcz_proj/synthesis/./../compile/ukladsterujacy.vhd in Library work.
Architecture ukladsterujacy_arch of Entity ukladsterujacy is up to date.
Compiling vhdl file e:/projekty_vhdl/miroslawcz_proj/miroslawcz_proj/synthesis/./../src/ukladoperacyjny.vhd in Library work.
Architecture ukladoperacyjny of Entity ukladoperacyjny is up to date.
Compiling vhdl file e:/projekty_vhdl/miroslawcz_proj/miroslawcz_proj/synthesis/./../src/przetworzenie.vhd in Library work.
Architecture przetworzenie of Entity przetworzenie is up to date.
Compiling vhdl file e:/projekty_vhdl/miroslawcz_proj/miroslawcz_proj/synthesis/./../compile/calyuklad.vhd in Library work.
Architecture calyuklad of Entity calyuklad is up to date.
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <calyuklad> (Architecture <calyuklad>).
Entity <calyuklad> analyzed. Unit <calyuklad> generated.
Analyzing Entity <ukladsterujacy> (Architecture <ukladsterujacy_arch>).
Set property "fsm_extract = yes" for signal <Sreg0>.
Set property "fsm_fftype = d" for signal <Sreg0>.
Entity <ukladsterujacy> analyzed. Unit <ukladsterujacy> generated.
Analyzing Entity <ukladoperacyjny> (Architecture <ukladoperacyjny>).
Entity <ukladoperacyjny> analyzed. Unit <ukladoperacyjny> generated.
Analyzing Entity <przetworzenie> (Architecture <przetworzenie>).
Entity <przetworzenie> analyzed. Unit <przetworzenie> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <przetworzenie>.
Related source file is e:/projekty_vhdl/miroslawcz_proj/miroslawcz_proj/synthesis/./../src/przetworzenie.vhd.
Unit <przetworzenie> synthesized.
Synthesizing Unit <ukladoperacyjny>.
Related source file is e:/projekty_vhdl/miroslawcz_proj/miroslawcz_proj/synthesis/./../src/ukladoperacyjny.vhd.
WARNING:Xst:647 - Input <rst> is never used.
WARNING:Xst:643 - The result of a 4x4-bit multiplication found at line 41 is partially used. Only the 7 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
Found 4x4-bit multiplier for signal <$n0000> created at line 41.
Summary:
inferred 1 Multiplier(s).
Unit <ukladoperacyjny> synthesized.
Synthesizing Unit <ukladsterujacy>.
Related source file is e:/projekty_vhdl/miroslawcz_proj/miroslawcz_proj/synthesis/./../compile/ukladsterujacy.vhd.
Found finite state machine <FSM_0> for signal <Sreg0>.
-----------------------------------------------------------------------
| States | 10 |
| Transitions | 17 |
| Inputs | 6 |
| Outputs | 4 |
| Clock | clk (rising_edge) |
| Reset | rst (positive) |
| Reset type | asynchronous |
| Reset State | s1 |
| Power Up State | s1 |
| Encoding | automatic |
| Implementation | LUT |
-----------------------------------------------------------------------
Summary:
inferred 1 Finite State Machine(s).
Unit <ukladsterujacy> synthesized.
Synthesizing Unit <calyuklad>.
Related source file is e:/projekty_vhdl/miroslawcz_proj/miroslawcz_proj/synthesis/./../compile/calyuklad.vhd.
Unit <calyuklad> synthesized.
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Advanced RAM inference ...
Advanced multiplier inference ...
INFO:Xst:1784 - HDL ADVISOR - Multiplier(s) is(are) identified in your design. You can improve the performance of your multiplier by using the pipeline feature available with mult_style attribute.
Advanced Registered AddSub inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <Sreg0> with one-hot encoding.
Dynamic shift register inference ...
=========================================================================
HDL Synthesis Report
Macro Statistics
# FSMs : 1
# Multipliers : 1
4x4-bit multiplier : 1
# Registers : 10
1-bit register : 10
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <calyuklad> ...
Optimizing unit <przetworzenie> ...
Loading device for application Xst from file 'v50.nph' in environment D:/Xilinx.
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block calyuklad, actual ratio is 2.
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : calyuklad.ngr
Top Level Output File Name : calyuklad
Output Format : NGC
Optimization Goal : speed
Keep Hierarchy : no
Design Statistics
# IOs : 19
Macro Statistics :
# Multipliers : 1
# 4x4-bit multiplier : 1
Cell Usage :
# BELS : 70
# GND : 1
# LUT2 : 11
# LUT2_L : 1
# LUT3 : 3
# LUT3_L : 3
# LUT4 : 15
# LUT4_L : 3
# MULT_AND : 8
# MUXCY : 13
# XORCY : 12
# FlipFlops/Latches : 10
# FDC : 9
# FDP : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 18
# IBUF : 11
# OBUF : 7
=========================================================================
Device utilization summary:
---------------------------
Selected Device : v50bg256-6
Number of Slices: 21 out of 768 2%
Number of Slice Flip Flops: 10 out of 1536 0%
Number of 4 input LUTs: 36 out of 1536 2%
Number of bonded IOBs: 18 out of 184 9%
Number of GCLKs: 1 out of 4 25%
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 10 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -6
Minimum period: 5.280ns (Maximum Frequency: 189.394MHz)
Minimum input arrival time before clock: 3.814ns
Maximum output required time after clock: 20.232ns
Maximum combinational path delay: 12.655ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay: 5.280ns (Levels of Logic = 2)
Source: U1_Sreg0_FFd1 (FF)
Destination: U1_Sreg0_FFd10 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: U1_Sreg0_FFd1 to U1_Sreg0_FFd10
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 4 1.065 1.440 U1_Sreg0_FFd1 (U1_Sreg0_FFd1)
LUT4:I0->O 1 0.573 1.035 U1_Sreg0_FFd10-In12 (CHOICE98)
LUT2_L:I1->LO 1 0.573 0.000 U1_Sreg0_FFd10-In13 (U1_Sreg0_FFd10-In)
FDP:D 0.594 U1_Sreg0_FFd10
----------------------------------------
Total 5.280ns (2.805ns logic, 2.475ns route)
(53.1% logic, 46.9% route)
-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset: 3.814ns (Levels of Logic = 3)
Source: x1 (PAD)
Destination: U1_Sreg0_FFd10 (FF)
Destination Clock: clk rising
Data Path: x1 to U1_Sreg0_FFd10
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 0.768 1.206 x1_IBUF (x1_IBUF)
LUT4_L:I1->LO 1 0.573 0.100 U1_Sreg0_FFd10-In7 (CHOICE95)
LUT2_L:I0->LO 1 0.573 0.000 U1_Sreg0_FFd10-In13 (U1_Sreg0_FFd10-In)
FDP:D 0.594 U1_Sreg0_FFd10
----------------------------------------
Total 3.814ns (2.508ns logic, 1.306ns route)
(65.8% logic, 34.2% route)
-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset: 20.232ns (Levels of Logic = 13)
Source: U1_Sreg0_FFd7 (FF)
Destination: t<6> (PAD)
Source Clock: clk rising
Data Path: U1_Sreg0_FFd7 to t<6>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 5 1.065 1.566 U1_Sreg0_FFd7 (U1_Sreg0_FFd7)
LUT4:I2->O 1 0.573 1.035 U1_Sreg0_Out316 (CHOICE87)
LUT3:I2->O 1 0.573 1.035 U1_Sreg0_Out335_SW0 (N1719)
LUT4:I3->O 4 0.573 1.440 U1_Sreg0_Out335 (BUS294<0>)
LUT4:I0->O 5 0.573 1.566 U3_z<2>1 (NET286<2>)
LUT2:I0->O 1 0.573 0.000 U2_Mmult__n0000_inst_lut2_21 (U2_Mmult__n0000_inst_lut2_2)
MUXCY:S->O 1 0.653 0.000 U2_Mmult__n0000_inst_cy_5 (U2_Mmult__n0000_inst_cy_5)
MUXCY:CI->O 1 0.044 0.000 U2_Mmult__n0000_inst_cy_6 (U2_Mmult__n0000_inst_cy_6)
MUXCY:CI->O 1 0.044 0.000 U2_Mmult__n0000_inst_cy_7 (U2_Mmult__n0000_inst_cy_7)
XORCY:CI->O 1 0.418 1.035 U2_Mmult__n0000_inst_sum_8 (U2_Mmult__n0000_N444)
LUT2:I1->O 1 0.573 0.000 U2_Mmult__n0000_inst_lut2_71 (U2_Mmult__n0000_inst_lut2_7)
MUXCY:S->O 0 0.653 0.000 U2_Mmult__n0000_inst_cy_13 (U2_Mmult__n0000_inst_cy_13)
XORCY:CI->O 1 0.418 1.035 U2_Mmult__n0000_inst_sum_14 (t_6_OBUF)
OBUF:I->O 4.787 t_6_OBUF (t<6>)
----------------------------------------
Total 20.232ns (11.520ns logic, 8.712ns route)
(56.9% logic, 43.1% route)
-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay: 12.655ns (Levels of Logic = 12)
Source: a<0> (PAD)
Destination: t<6> (PAD)
Data Path: a<0> to t<6>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 5 0.768 1.566 a_0_IBUF (a_0_IBUF)
LUT2:I1->O 2 0.573 0.000 U2_Mmult__n0000_inst_lut2_01 (U2_Mmult__n0000_inst_lut2_0)
MUXCY:S->O 1 0.653 0.000 U2_Mmult__n0000_inst_cy_0 (U2_Mmult__n0000_inst_cy_0)
MUXCY:CI->O 1 0.044 0.000 U2_Mmult__n0000_inst_cy_1 (U2_Mmult__n0000_inst_cy_1)
MUXCY:CI->O 1 0.044 0.000 U2_Mmult__n0000_inst_cy_2 (U2_Mmult__n0000_inst_cy_2)
MUXCY:CI->O 1 0.044 0.000 U2_Mmult__n0000_inst_cy_3 (U2_Mmult__n0000_inst_cy_3)
XORCY:CI->O 1 0.418 1.035 U2_Mmult__n0000_inst_sum_4 (U2_Mmult__n0000_N424)
LUT2:I0->O 1 0.573 0.000 U2_Mmult__n0000_inst_lut2_61 (U2_Mmult__n0000_inst_lut2_6)
MUXCY:S->O 1 0.653 0.000 U2_Mmult__n0000_inst_cy_12 (U2_Mmult__n0000_inst_cy_12)
MUXCY:CI->O 0 0.044 0.000 U2_Mmult__n0000_inst_cy_13 (U2_Mmult__n0000_inst_cy_13)
XORCY:CI->O 1 0.418 1.035 U2_Mmult__n0000_inst_sum_14 (t_6_OBUF)
OBUF:I->O 4.787 t_6_OBUF (t<6>)
----------------------------------------
Total 12.655ns (9.019ns logic, 3.636ns route)
(71.3% logic, 28.7% route)
=========================================================================
CPU : 2.09 / 2.94 s | Elapsed : 3.00 / 3.00 s
-->
Total memory usage is 57464 kilobytes
Processing design ...
Writing file calyuklad.vhd completed.
Synthesis finished with warnings.
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