32 bitowe mikrokontrolery rodziny AVR

Dariusz Chaberski

AT32AP7000

§ Blockdiagram

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§ NGW 100

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§ Overview of the AVR32 AP CPU

TLB - Translation lookaside buffer

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§ The AVR32 AP Pipeline

IF1, IF2 - Instruction Fetch stage 1 and 2

ID - Instruction Decode

IS - Instruction Issue

A1, A2 - ALU stage 1 and 2

M1, M2 - Multiply stage 1 and 2

DA - Data Address calculation stage

D - Data cache access

WB - Writeback

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§ Overview of execution modes, their priorities and privilege levels

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§ Entry and exit from states, modes and functions

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§ Register File in AVR32A

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§ Register File in AVR32B

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§ A typical AVR32B register file implementation

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§ The Status Register High Halfword

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§ The Status Register Low Halfword

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§ Data representation in the register file

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§ Instructions storage in memory (big endian fashion)

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§ Java Extension Module

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§ AVR32 Java Virtual Machine and the Java Extension Module

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§ Example of running a Java program

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§ Arithmetic Operations

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§ Multiplication Operations

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§ DSP Operations

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§ Logic Operations

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§ Bit Operations

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§ Shift Operations

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§ Instruction Flow

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§ Move/Load Immediate Operations

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§ Load/Store Operations

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§ Mutiple data

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§ System/Control

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§ Coprocessor Interface

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§ Instructions to aid Java execution

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§ SIMD Operations

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§ Memory read-modify-write Instructions

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§ Pixel Coprocessor (PICO)

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Vector Multiplication Unit (VMU)

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Input Pixel Selector - Transformation Mode

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Input Pixel Selector - Horizontal Filter Mode Pixel Addressing

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Input Pixel Selector - Vertical Filter Mode Pixel Addressing

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Output Pixel Inserter - Planar Pixel Insertion

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Output Pixel Inserter - Packed Pixel Insertion

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PICO Register File

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PICO instruction summary

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§ Memories

+ Embedded Memories

3 2 x 16 Kbyte SRAM

3 Single cycle access at full bus speed

+ Physical Memory Map

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HSB masters

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HSB slaves

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§ Real Time Counter (RTC)

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RTC Control

PSEL - Prescale Select

TOPEN - Top Enable

PCLR - Prescaler Clear

EN - Enable

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§ Watchdog Timer (WDT)

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WDT Control

KEY - 0x55, 0xAA

PSEL - Prescale Select

EN - WDT Enable

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§ Interrupt Controller (INTC)

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INTC address map

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Interrupt Request Registers

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Interrupt Priority Registers

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Interrupt Cause Registers

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§ External Interrupt Controller (EIC)

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User Interface

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EIC Interrupt Enable/Disable/Mask/Status/Clear

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External Interrupt Mode/Edge/Level

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NMI Control

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§ External Bus Interface (EBI)

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I/O Lines Description

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EBI Connections to Memory Devices

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§ DMA Controller (DMACA)

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DMACA Transfer Hierarchy for Non-Memory Peripheral

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DMACA Transfer Hierarchy for Memory

a peripheral should be assigned as memory only if it does not insert more than 16 wait states

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Multi-block Transfer Using Linked Lists

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Multi-Block with Linked List Address for Source and Destination

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Multi-Block with Linked Address for Source and Destination Blocks are Contiguous

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Multi-Block DMA Transfer with Source and Destination Address Auto-reloaded

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Multi-Block DMA Transfer with Source Address Auto-reloaded and Linked List Destination Address

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Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address

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DMA Transfer with Linked List Source Address and Contiguous Destination Address

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Channel x Source Address Register

The address offset for each channel is: [x *0x58]

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Channel x Destination Address Register

The address offset for each channel is: 0x08+[x * 0x58]

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Linked List Pointer Register for Channel x

The address offset for each channel is: 0x10+[x * 0x58]

LMS - List Master Select

LOC - Address of the next LLI

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§ Peripheral DMA Controller (PDC)

R/THR Receive/Transmit Holding Register

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§ Serial Peripheral Interface (SPI)

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§ Two-wire Interface (TWI)

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§ Synchronous Serial Controller (SSC)

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I/O Lines Description

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SSC Functional Block Diagram

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Transmit Start Mode

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Receive Pulse/Edge Start Modes

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§ Universal Synchronous/Asynchronous Receiver/Transmitter (USART)

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Hardware Handshaking

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Receiver Behavior when Operating with Hardware Handshaking

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Transmitter Behavior when Operating with Hardware Handshaking

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§ AC97 Controller (AC97C)

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Application Block Diagram

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Bidirectional AC-link Frame with Slot Assignment

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AC-link Output Slots Transmitted from the AC97C Controller

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AC-link Input Slots Transmitted from the AC97C Controller

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§ Audio Bitstream DAC (ABDAC)

Equalization Filter - 3-tap FIR filter

Interpolation filter - interpolation from fs to 128fs

Sigma Delta Modulator - 3rd order Sigma Delta Modulator

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Frequecy response, EQ-FIR+COMB4

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§ Static Memory Controller (SMC)

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SMC Connections to Static Memory Devices

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§ SDRAM Controller (SDRAMC)

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SDRAM Controller Connections to SDRAM Devices: 32-bit Data Bus Width

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SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns

SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns

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SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns

M[1:0] - byte address inside a 32-bit word

Bk[1:0] - Bank Select Signals

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SDRAM Controller Connections to SDRAM Devices: 16-bit Data Bus Width

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SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns

SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns

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SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns

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Write Burst, 32-bit SDRAM Access

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Read Burst, 32-bit SDRAM Access

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Read Burst with Boundary Row Access

RAS=0, SDWE=0 - precharge command

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Refresh Cycle Followed by a Read Access

RAS=0, CAS=0 - Refresh Cycle Initialization

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§ Error Corrected Code (ECC) Controller

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Parity Generation for 512/1024/2048/4096 8-bit Words

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Calculation of P8’ to PX’ and P8 to PX

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Parity Generation for 512/1024/2048/4096 16-bit Words

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Calculation of P8’ to PX’ and P8 to PX

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§ MultiMedia Card Interface (MCI)

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MultiMedia Memory Card Bus Topology

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SD Memory Card Bus Signals

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Mixing MultiMedia and SD Memory Cards with Two Slots

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§ Ethernet MAC (MACB)

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Receive Buffer List

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§ Timer/Counter (TC)

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Clock Selection

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Clock Control

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Capture Mode

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Waveform Mode

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§ Pulse Width Modulation Controller (PWM)

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§ Image Sensor Interface (ISI)

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HSYNC and VSYNC Synchronization

SAV and EAV Sequence Synchronization

S/EAV - Start/End of Active Video

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Data Ordering in YCbCr Mode

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RGB Format in Default Mode, RGB CFG = 00, No Swap

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RGB Format, RGB CFG = 10 (Mode 2), No Swap

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RGB Format in Default Mode, RGB CFG = 00, Swap Activated

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Preview Path

Decimation Factor

Decimation and Scaler Offset Values

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Resize Examples

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Color Space Conversion

Preview Path (YCrCb or YUV to RGB)

Codec Path (RGB to YCrCb)

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§ On-Chip Debug

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JTAG-based debugger

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AUX+JTAG based debugger

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Auxiliary port signals

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§ JTAG and Boundary Scan

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§ Hi-Speed USB Interface (USBA)

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USBA Endpoint Description

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Board Schematic

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§ LCD Controller (LCDC)

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