Mikrokontrolery rodziny 8051

Dariusz Chaberski

8051

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§ PDIP package

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§ Memory Structure

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§ Program Memory

z

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§ Executing from External Program Memory

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§ Accessing External Data Memory

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§ Internal Data Memory

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§ Lower 128 Bytes of Internal RAM

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§ Upper 128 Bytes of Internal RAM (8052 Extension)

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§ SFR Space

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§ Program Status Word

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§ State Sequence

+ 1-byte, 1-cycle Instruction, e.g., INC A

+ 2-byte, 1-cycle Instruction, e.g., ADD A,#data

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§

+ 1-byte, 2-cycle Instruction, e.g., INC DPTR

+ MOVX (1-byte, 2-cycle)

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§ Bus Cycles in 80C51 Family Devices Executing from External Program Memory

+ Without a MOVX

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§

+ With a MOVX

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§ Interrupt Enable (IE) Register

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§ Interrupt Priority (IP) Register

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§ Interrupt Control System

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§ SFR Memory Map

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§ 80C51 Port Bit Latches and I/O Buffers

+ Port 0 Bit

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§

+ Port 1 Bit

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§

+ Port 2 Bit

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§

+ Port 3 Bit

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§ Timer/Counter Mode 0: 13-Bit Counter

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§ Timer/Counter Mode 2: 8-Bit Auto-Load

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§ Timer/Counter 0 Mode 3: Two 8-Bit Counters

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§ instrukcje

+ operacje arytmetyczne

ADD A, Rn/adr/@Ri/#dana - A=A+Rn/(adr)/(Ri)/#dana

ADDC A, Rn/adr/@Ri/#dana - A=A+Rn/(adr)/(Ri)/#dana+C

SUBB A, Rn/adr/@Ri/#dana - A=A-Rn/(adr)/(Ri)/#dana-C

INC A/Rn/adr/@Ri/DPTR - A/Rn/(adr)/(Ri)/DPTR=A/Rn/(adr)/(Ri)/DPTR+1

DEC A/Rn/adr/@Ri - A/Rn/(adr)/(Ri)=A/Rn/(adr)/(Ri)-1

MUL AB - B:A=A*B

DIV AB - A=Int(A/B), B=Mod(A/B)

DA - if((A(3..0)>9) || AC==1) A(3..0)=A(3..0)+6, if((A(7..4)>9) || CY==1) A(7..4)=A(7..4)+6

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§

+ operacje logiczne

ANL A, Rn/adr/@Ri/#dana - A=A&Rn/(adr)/(Ri)/#dana

ANL adr, A/#dana - (adr)=(adr)&A/#dana

ORL A, Rn/adr/@Ri/#dana - A=A|Rn/(adr)/(Ri)/#dana

ORL adr, A/#dana - (adr)=(adr)|A/#dana

XRL A, Rn/adr/@Ri/#dana - A=AˆRn/(adr)/(Ri)/#dana

XRL adr, A/#dana - (adr)=(adr)ˆA/#dana

CLR A - A=0

CPL A - A=0xFF-A

RL A - A(n+1)=A(n), A(0)=A(7)

RLC A - A(n+1)=A(n), n=0..6, A(0)=C, C=A(7)

RR A - A(n)=A(n+1), A(7)=A(0)

RRC A - A(n)=A(n+1), n=0..6, A(7)=C, C=A(0)

SWAP A - A(7..4)<->A(3..0)

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§

+ rozkazy przesłań

MOV A, Rn/adr/@Ri/#dana - A=Rn/(adr)/(Ri)/#dana

MOV Rn, A/adr/#dana - Rn=A/(adr)/#dana

MOV adr, A/Rn/adr1/@Ri/#dana - (adr)=A/Rn/(adr1)/(Ri)/#dana

MOV @Ri, A/adr/#dana - (Ri)=A/(adr)/#dana

MOV DPTR,#dana 16 - DPTR=#dana 16

MOVC A, @A+DPTR/@A+PC - A=(A+DPTR)/(A+PC)

MOVX A, @Ri/@DPTR - A=(256*P2+Ri)/(DPTR)

MOVX @Ri/@DPTR, A - (256*P2+Ri)/(DPTR)=A

XCH A, Rn/adr/@Ri - A<->Rn/(adr)/(Ri)

XCHD A, @Ri - A(3..0)<->(Ri)(3..0)

PUSH adr - SP=SP+1, (SP)=(adr)

POP adr - (adr)=(SP), SP=SP-1

NOP

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§

+ instrukcje bitowe

MOV C, bit - C=bit

MOV bit, C - bit=C

CLR C/bit - C/bit=0

SETB C/bit - C/bit=1

CPL C/bit - C/bit=1-C/bit

ANL C, bit/(1-bit) - C=C&bit/(1-bit)

ORL C, bit/(1-bit) - C=C|bit/(1-bit)

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§

+ Skoki i wywołania podprogramów

AJMP adr 11

LJMP adr 16

SJMP rel

JMP @A+DPTR - PC=A+DPTR

JC/JNC/JZ/JNZ rel

JB/JNB/JBC bit, rel

CJNE A, adr/#dana, rel

CJNE Rn/@Ri, #dana, rel

DJNZ Rn/adr, rel

ACALL adr 11

LCALL adr 16

RET

RETI

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ADuC 812

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§ QFP package

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§ Program and Data Memory Maps

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§ Internal ADC Structure

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§ ADC Result Format

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§ Typical DMA External Memory Preconfiguration

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§ Typical External Memory Configuration Post ADC DMA Operation

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§ DMA Cycle

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§ Timer/Counter 2, 16-Bit Autoreload Mode

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§ Timer/Counter 2, 16-Bit Capture Mode

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§ External Data Memory Interface (16 M Bytes Address Space)

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CY7C 68013

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§ QFP package

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§ FX2 Block Diagram

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§ FX2 Block Diagram

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§ FX2 to Standard 8051 Timing Comparison

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§ Special Function Registers

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§ Internal Code Memory, EA = 0

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§ External Code Memory, EA = 1

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§ Register Addresses

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§ Endpoint Configurations (High-speed Mode)

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§ Default High-Speed Alternate Settings

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§ GPIF’s Place in the FX2 System

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§ USB Interrupts

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§ The USB Autovector Mechanism in Action

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§ EP2/4/6/8CFG - Endpoint 2/4/6/8 Configuration (E612-E615)

VALID: 1 = activate

DIR: 0 = OUT, 1 = IN

TYPE

SIZE: 0 = 512 bytes, 1 = 1024 bytes

BUF

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§ EP2/4/6/8CS Endpoint 2/4/6/8 Control and Status (E6A3-E6A6)

NPAK2:0: Number of Packets in FIFO

FULL: Endpoint FIFO Full

EMPTY: Endpoint FIFO Empty

STALL: ENDPOINT STALL

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§ EP2468STAT Endpoint(s) 2,4,6,8 Status Flags (SFR 0xAA)

SFR and FX2 Register File Correspondences

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§ EP2/6BCH Endpoint 2/6 Byte Count HIGH (E690/E698)

§ EP4/8BCH Endpoint 4/8 Byte Count HIGH (E694/E69C)

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§ EP2/4/6/8BCL Endpoint 2/4/6/8 Byte Count LOW (E691,E695,E699, E69D)

EP2BCL = 0x01;

// commit newly sourced pkt. to interface fifo

EP2BCL = 0x80;

// arm EP2OUT by writing to the byte count w/skip

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