Servive, Engineering & Optimization

2005.12.15

LEVEL 3 AL Block Diagram

Rev. 1.5

U6 Pebble

Alexander Buehler, Michael Mauderer

Page 1of 2

U6 Pebble

OSCO_F

3

3

2

2

1

1

LNA

LNA

LNA

A2

TX_OUT_HB

DCS/PCS OUT

GSM850/

BP

7

5

2

9

GSM900 OUT

GMSK/ EDGE Select

L

oop

Filter

RX/TX
Switch

ADC
13 bit

Sync
Filter

Anti
Drop

Anti
Alias

RX/TX
Switch

ADC
13 bit

Sync
Filter

Anti
Drop

Anti
Alias

Chanel
Filter

DAC
12 bit

LPF

Chanel
Filter

DAC
12 bit

LPF

Serial
Interface

Ser

ial

In

te

rface

GMSK
Modulator

EDGE
Modulator

EDGE
FIR
Filter

Anti
Alias

Pre-Distortion
Filter

Devider

PA Control

F8

F7

F6

H7

16

U50
PA + Antenna Switch

21

4 6

FIN

ENR

CLKR

FSR

DRI

IIN

IBIN

QBIN

G4

F4
F5

G3

LDTO

TX

I

MS

MD

I

MC

LK

D7

E8

E7

G8

RA

MP

TX_EN

VCO2 (TX_HB)

VCO1 (TX_LB)

U250

GSM/ EDGE

from Neptune

Y201

26MHz

2

1

1800 MHz

1900 MHZ

850 MHz

900 MHz

(P

A P

o

wer

Contr

o

l)

M1201

Mechanical

Antenna Switch

Output M

ixer

Digital TX

Interface

U51

U52

Internal
Antenna

M3

RX_

AN

T_E

N

CNT

RL

_2

CNT

RL

_3

TX_

S

T

A

R

T

OSCO

OSCM

PERIPH_IO_REG

D8

E5

G7

O

sci

la

to

r and

C

loc

k G

en

er

at

o

r

(N

C)

(T

ra

ns

m

itt E

n

able)

MS
MDI

MCLK

RF_CLK

RF_DATA

RF_CS

( VCO Feedback )

( VCO Tuning)

(100KHz)

( Lock Detect Out)

C3

DAC1

(to U200)

C2

D6 G5

E6

GPIO

CP

Phase Det.

(U250 Control Bus)

( Frontend Control
and Digital Modulation)

ADC
Voltage
Reg.

VCO_REG
PERIPH_IO_REG
RF_REG

H3

G7..
C1..

(VCC’s from Atlas)

A4

1Mbit RAM

DSP

DSP

UltraLite
104 MHz

DSP Peripherals
accelerator, encryption
Timer, Interupts

Shared Memory

MCU

52 MHz

ARM7

MCU

26 MHz
Oscillator

Memory

Memory

SIM

Interface

External

Interface

Memory

W7

Clock Generator

SPI

Power

NEPTUNE LTS

U800

G12

A13

N10

VoiceBand

L1 Timer

V8

U6

U8
V7
W9

SPI

T9

W10

U9

UART / USB

Interface

Keypad
Interface

On

Off

2

1

6

SIM DIO

SIM RST

SIM CLK
SIM_PD

3

VSIM

4

GND

Connector

M1200

SIM

1.8 or 3V
SIM Card

VSIM_EN

VBUCK

(VCC + 1,875V)

(from PCAP )

VSIM

(to Pcap)

IO_REG

J4
L1

K3

R1
M1

K2

(from PCAP )

(from Atlas )

5

PERIPH_IO_REG

( to

Atlas

)

TX

_S

T

A

R

T

(100KHz)

EGSM: CH 37 -- 942,4Mhz

DCS: CH 700 -- 1842,8MHz

PCS: CH 661 -- 1960MHz

RX MID CHANNELS

GSM: CH 62 -- 947,4 MHz

850: CH190 -- 881,6

MQSPI
Display

U700

EB1B

EB0B

OEB

R WB

CS1B

ADDRESS BUS

DATA BUS

K16

J19

G17

T16

BURSTCLK

LBAB

CE_1

ECBB

V17

T19
L16

N18

A1-24

D0-15

32 MB Flash

RESET OUT

F3
C2

D6

E5

F5,D5
J2,H1,H8

G7

C6

K1

F4

G8

HS INT

C14

(Flip Open/ Close

Detect)

ADC DATA

E1

DS1500

LT_SNS_CTL

1

6

2

Light Sensor

8MB SRam

(from Neptune)

FLASH

U13

BB

_SA

P

_T

X

B

B

_

S

AP

_R

X

BB

_SA

P

_

F

S

BB

_S

A

P

_

C

LK

B13

B12

A12

D13

(fram

es

y

n

c)

(cl

o

ck)

CLK

13 MH

z

W13

C15

C16

D15

A16

BB

_

S

P

I_C

LK

BB

_S

PI_M

O

S

I

B

B

_S

PI_

M

IS

O

AU

L_

CS

Neptune Atlas

Communication

T11

V12

V11

W12

ST

AN

DB

Y_1

_5V

G8

ST

A

N

DB

Y

CL

K 32

KH

Z

E3

B14

AU

L_

INT

RE

SET

B

V13

(13 M

H

z)

(W

a

tc

h

dog)

WD

OG

OW

B

W11

O

n

e W

ire d

at

a from

B

at

ter

y

US

B_V

P

IN

U

S

B

_

XR

XD

_

R

T

S

US

B_V

P

O

U

T

_

TX

D

US

B_V

M

IN_R

XD

U

S

B

_

TX

EN

B

US

B_S

E

0

B16

A17

Neptune Atlas

USB/ RS232

Communication

(f

ro

m

/to

A

tl

a

s

RE

SET

O

U

T

W5

(t

o U700)

(from/ to Neptune

Serial Audio for Ringtone

and Voice Audio)

RX

D2

TX

D2

RT

S

2

CT

S

2

N17

N13

V16

D16

(from/ to U301 BT, J1300

Neptune - BT - Neptune

Communication and Wakeup)

BLU

E_

W

A

KE

B

B

L

UE

_H

OS

T_W

A

K

E

B

D19

B15

KB

R0

-7

KB

C

0

-1

F3....

G3....

GR

AP

H_S

PI_

C

S

D18

Neptune Display Diver

Timer

GPIO

Interface

BaseBand

Port Interface

Serial Audio

(tx)

(rx)

MQSPI

One

Bus

Wire

UART2

Universal

Asynchron.

Rx /Tx

BT

CE_2

W18

C18

V6

STANDBY_GATEB

T10

G

RAP

H_

INT

ST

AN

DB

Y_

G

A

TE

B

OS

CM

U802

1

2

4

(t

o Atlas

)

TRANCEIVER

QIN

SAW/ LNA

Matching

SAW/ LNA

Matching

SAW/ LNA

Matching

SAW/ LNA

Matching

3

CNT

RL

_1

B7

TX

_E

N

15

14

13

Power and
Antenna
Control

(B

and

s

elect)

8

D2

Reference
Devider

(Clock enable)

3

C5

C6

Polyphase
Filter

DC
Correct

Quadrature
Generator

Quadrature
Mixer

LNA

TX_OUT_LB

G1

F1

A3

A5

A6

(NC)

(f

ro

m Neptune GP

IO

)

2

4

(from

At

la

s)

(NC)

VBUCK

E4...

(from

Atlas

)

U801

Level

(to

A

tl

as)

P2

LCD_RS

P1

LCD_SDATA_DATA7

M4

LCD_CLK_DATA6

N3

LCD_CS

L3...

LCD DATA (0 - 5)

A14

(to Clock enable Circuit)

(LCD Control via J1300)

KEYPAD

MATRIX

0-9,*,#,
Up, Down
Left-Right,
Center,
Soft L+R,
Menu, Send,
Volume U-D
Smart, VA

SJ

C_

M

O

D

A15

FL

1404
ESD

FL

1405
ESD

Customer
Clear

VSIM

(from Atlas)

2

1

2

1

U1600

U1601

4

2

Reg.

Hall Effect

Switch

PERIPH_IO_REG

6

1

Shift

an

d

BT

))

(VCC + 1,575V)

REF_REG

E2

A

TI_

RES

E

T

T13

(t

o

J1

300

)

(VCC + 2.775V)

A11

(VCC + 2.775V)

H1

V5

TOUT12

U10

(Bias output for THERM signal)

(Clock )

(Reset )

(Data In /OUT)

( Frontend Control

and Digital Modulation)

(R

eceive E

n

able)

(T

rans

mit

t E

n

abl

e

)

(Clock )

(Reset )

(Data In /OUT)

(Clock )

(Chip select)

(Data In /OUT)

Revision Overview
Rev. 1.0: Initial Block Diagram
Rev.1.1 Add Bias Voltage at THERM signal.
Rev. 1.2 updated Atlas Audio Interface
Rev.1.3 renamed to U6
Rev. 1.4: Updated Charger logic levels
Rev.1.5: Updated Atlas Stereo Codec

Servive, Engineering & Optimization

2005.12.15

LEVEL 3 AL Block Diagram

Rev. 1.5

U6 Pebble

Alexander Buehler, Michael Mauderer

Page 2of 2

(clock)

CLK 13 MHZ

V12

CLK_32KHZ_2_7V

P16

TIMER

WDOG

K10

CNTL.

PRI SPI

LOGIC

Logic

F

3

,E

1

3

...

..

...

S

w

itcher

BB-

SPI

_

CL

K

BB

_S

P

I_

M

OS

I

B

B

_

S

PI

_M

ISO

AU

L CS

U18

U1

6

T1

8

T1

7

R5

Y900

V17

D12

RTC_BATT

V16

BP

HAND_SPKRM

HAND_SPKRP

T6
R7

T9

P9

V10

U8

PW

R SW

F1

4

B4

E3

F3

U900

ATLAS UL

ON

LOGIC

OWB

THERM

P13

THERM

ISNS

BATTP

D14
F13

GND

CHRGCTRL

B16

VBUS

S

G

D

CHARGE

CHARGER

BATT CONN.

CNTL.

LED

E12

BATTERY

B

B

SA

P FS

BB

SAP

C

L

K

BB S

A

P TX

BB SA

P RX

Neptune Atlas

CODEC

16 BIT

STEREO

Communication

ALERTM

ALERTP

STANDBY

F12

(to Neptune and U301 BT)

AU

L_I

N

T

N1

4

RESETB

(from U801)

Neptune PCap

Communication

USB_ID

H8

Q904

G

S

BP

B12

BATTFET

Battery to BPLUS

USB

V

P

IN

U

S

B XR

XD

R

T

S

U

S

B VP

OU

T TX

D

U

S

B VM

IN

R

X

D

U

S

B TX

EN

B

USB

S

E

0

USB/RS232

(communication)

B2

C4

F4

B1

B3

E4

MICINM

MICBIAS1

B

oos

t 300m

A

G16

S

w

itcher

B

u

c

k

350mA

F16

( 1,

87

5V )

VB

U

C

K

H2

( 2,

7

75V

)

PE

RIP

H

_

IO RE

G

U6

( 2,

77

5V

)

AUD

_ RE

G

M1

8

( 1,

2

75 )

GR

AP

H

_

R

E

G

K17

H4

H3

( 2,

7

75V

)

RF

_RE

G

L16

( 1

,57

5V

)

RE

F_R

E

G

N5

( 1,

8/

3V

)

VSI

M

VS

IM

V

S

IM

_E

N

K1

1

VBUS

CONTR.

E7

L10

AD

(VBUS)

C15

IO

R

E

G

(B

ia

s)

(One Wire Bus

to Neptune)

BPFET

VBUS to BP

Switch

(Main Source

for Atlas)

(from Acesory Connector)

Main Charge Path

B+ support without Ext Charger
B+ support with Ext Charger

Color definition only for this section !

D902

BB_SAP_TX

BB_SAP_RX

BB_SAP_FS

BB_SAP_CLK

(framesync)

Bluetooth

U301

32

30

28

27

BLUE_WAKEB

11

BLUE_HOST_WAKEB

9

TXD2

5

CTS2
RTS2

31

RXD2

33
29

RESET_B

22

(from Neptune/ Atlas)

(from/ to Neptune

Serial Audio for Ringtone

and Voice Audio)

PERIPH_IO_REG

10

BTRF_REG

21

BT_ANTENNA

25

Strip Line

Antenna

(on PCB)

Y300

15

16

12

VVI

B

(t

o

V

ibra

tor P

ads

ne

ar

(from Neptune)

Neptune PCap

Neptune Atlas

USB/ RS232

Communication

D6
F8

(Battery Sense)

(VBUS Sense)

CONV.

D/A

CLK_32KHZ

(from Atlas)

J41

1

LS 1400

2
1

(from Atlas)

( 1,

3

V

)

POWER/END

(from/ to U301 BT,

Neptune - BT - Neptune

Communication and Wakeup)

Internal

MIC

Alert

Pads

Revision Overview
Rev. 1.0: Initial Block Diagram
Rev.1.1 Add Bias Voltage at THERM signal.
Rev. 1.2 updated Atlas Audio Interface
Rev.1.3 renamed to U6
Rev. 1.4: Updated Charger logic levels
Rev.1.5: Updated Atlas Stereo Codec

V30x, V400, V50x, V600

TX_START

U15

(from Neptune, Tx Mode indication for Atlas)

( 2,

7

75 )

IO

_R

EG

( 2,

77

5

)

EL

_SU

P

P

L

Y

( 5,

5

V

)

VB

OO

ST

U6 Pebble

U1501

EL-Lamp

Driver

EL_SUPPLY

EL_LAMP_V+

EL_EN

1

2,3

8

(~220Vpp)

7

EL_LAMP_V-

(to EL Backlight connection points-

left and right side of MENU button)

EL

Backlight

(from Atlas)

(from Neptune)

FL

1405
ESD

J1300

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34

GRAPH_REG
VBOOST
VBUCK

IO_REG
LCD_SDATA_DATA7
GND
LCD_CLK_DATA6

LCD_DATA2

RTC_BATT

GND

LCD_CS
DISP_LED2
GND
ATI_RESET
BB_SPI_CLK
VBUS
CHRGLED

HAND_SPKRM
HAND_SPKRP
LCD_DATA3
LCD DATA4
LCD DATA5
DISP_LED4
LCD_RS
GND
LCD_DATA1
GND
GND
CLK-32KHZ_2_7V
GND

GND
CLI_LED1

(from PCap 1,3V from Vibrator Regulator)

FLIP CONNECTOR

(from Neptune)

(from Atlas)

(from Neptune)

(from Neptune)

(from Neptune)

CLI_LED2
BB_SPI_MISO

J_USB

4
3

VBUS

5

2

1

(to Charging Circuit)

G1-G4

(Shield)

USB_ID

CLK_32KHZ

R16

DM_TXD

DP_RXD

VBOOST

VBUS

D2

(PPD device support)

1

3

35
37
39

BT_LED
GRAPH_INT
BB_SPI_MOSI

(from J1300)

g1- g4

GND

36
38
40

DISP_LED3
LCD_DATA0
GRAPH_SPI_CS

(from Neptune)

(from Neptune)

(from Atlas)

(from Neptune)

(from Atlas)

(from Atlas)

(from Neptune)

(from Atlas)

(from Neptune)

(from Atlas)

(from Neptune)

(to J1300)

C9

13

C9

36

to V

ib

rator

VIB

REG

P2

B+ Sense

Mo

to

r

Mi

ni

U

S

B

C

onn

ec

to

r)

REF REG

RF

REG

PE

RI

PH

IO

REG

AUD

IO

REG

IO REG

GR

A

P

H

RE

G

CAM

E

RA

REG

(only us

ed f

o

r E

L

C

rcui

t)

K2

( 1,

87

5V

)

BTR

F_

REG

BT R

E

G

4

(to J1300)

Q91

0

VCO

REG

VC

O_

REG

_

C

N

T

L

(M

ain S

our

ce-

f

ro

m

M

3

)

( 2,

77

5V

)

VC

O_

RE

G

V2

SIM_PD

T14

CHRGRAW

S

G

D Q903

Q905

(Current Sense)

G

S

M1400

2

3

1

4

R910

VR1201 / ESD

R924

D

Switch

B14

CHRGISNSP

E15

(Charger output

Sense)

(Current Control)

Q906

CHRGLED

DISP_LED4

CLI_LED2

DISP_LED3

(o

nly us

ed in Atlas

)

CLI_LED1

F6

E10

BT_LED

(t

o Neptune)

(A

tl

as

in

ter

n

al and

AL

cir

cuit)

( Atlas

, Neptun

e

,

U700,J

1300, L

evel Shif

ter

)

(t

o J

1

3

00)

(t

o Neptune amd M

120

0)

)

(t

o U250)

(t

o

U301)

(t

o Atlas

, Neptune, J

1300)

(t

o Atlas

and J

1300)

(t

o

U250)

Bluetooth

Flip Connector

Mini USB

Charger and Power-
source Control

EL Backlight
Supply

(toJ1300)

(from/ to Neptune and U700)

(toNeptune)

(from Atlas)

(from Neptune)

ESD

VR1301

VR1205

VR1204

TOUT12

(Bias Voltage from
Neptune)

(Accessory Detection signal)

(from Acesory Connector)

(EXT Power)

(EXT Power)

Interface

USB

Det.

Stereo

VBUS 5V

Pass FET

Microphone

R3

P4

R4

13 Bit

Handset

Amplifier

Det.

Headset

SAP

Supply

Amplifier

Alert

Amplifier

Headset

Amplifier

EMU

L

/

H

/

H

H

/

L

/

L

H

/

H

/

H

H

/

H

/

H

L

/

H

/

H

L

/

H

/

L