Xilinx System Settings Report System Settings   Environment Settings Environment Variable xst ngdbuild map par PATHEXT .COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.py;.pyw .COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.py;.pyw .COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.py;.pyw .COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.py;.pyw Path C:\Xilinx\14.2\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.2\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.2\ISE_DS\ISE\bin\nt;C:\Xilinx\14.2\ISE_DS\ISE\lib\nt;C:\Xilinx\Vivado\2012.2\bin;C:\Xilinx\14.2\ISE_DS\PlanAhead\bin;C:\Xilinx\14.2\ISE_DS\EDK\bin\nt;C:\Xilinx\14.2\ISE_DS\EDK\lib\nt;C:\Xilinx\14.2\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.2\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.2\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.2\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.2\ISE_DS\common\bin\nt;C:\Xilinx\14.2\ISE_DS\common\lib\nt;C:\Program Files\Common Files\Intel\Shared Files\cpp\bin\ia32;C:\Python27\;C:\Python27\Scripts;C:\WINDOWS\system32;C:\WINDOWS;C:\WINDOWS\System32\Wbem;C:\Program Files\Aldec\Active-HDL 8.2\BIN;C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;C:\Aldec\Active-HDL 8.3\BIN;C:\Impulse\CoDeveloper3\bin;C:\Impulse\CoDeveloper3\Libraries;C:\Impulse\CoDeveloper3\StageMaster\bin;C:\Impulse\CoDeveloper3\MinGW\bin;C:\Impulse\CoDeveloper3\MinGW\lib\gcc-lib\mingw32\3.3.1;C:\Cadence\SPB_16.5\tools\pcb\bin;C:\Cadence\SPB_16.5\tools\bin;C:\Cadence\SPB_16.5\tools\libutil\bin;C:\Cadence\SPB_16.5\tools\fet\bin;C:\Cadence\SPB_16.5\tools\specctra\bin;C:\Cadence\SPB_16.5\tools\PSpice;C:\Cadence\SPB_16.5\tools\PSpice\Library;C:\Cadence\SPB_16.5\tools\Capture;C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:\Program Files\MATLAB\R2011a\runtime\win32;C:\Program Files\MATLAB\R2011a\bin;C:\Aldec\Active-HDL 9.2\bin;C:\PROGRA~1\Motorola\DSP\dsp\bin C:\Xilinx\14.2\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.2\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.2\ISE_DS\ISE\bin\nt;C:\Xilinx\14.2\ISE_DS\ISE\lib\nt;C:\Xilinx\Vivado\2012.2\bin;C:\Xilinx\14.2\ISE_DS\PlanAhead\bin;C:\Xilinx\14.2\ISE_DS\EDK\bin\nt;C:\Xilinx\14.2\ISE_DS\EDK\lib\nt;C:\Xilinx\14.2\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.2\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.2\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.2\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.2\ISE_DS\common\bin\nt;C:\Xilinx\14.2\ISE_DS\common\lib\nt;C:\Program Files\Common Files\Intel\Shared Files\cpp\bin\ia32;C:\Python27\;C:\Python27\Scripts;C:\WINDOWS\system32;C:\WINDOWS;C:\WINDOWS\System32\Wbem;C:\Program Files\Aldec\Active-HDL 8.2\BIN;C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;C:\Aldec\Active-HDL 8.3\BIN;C:\Impulse\CoDeveloper3\bin;C:\Impulse\CoDeveloper3\Libraries;C:\Impulse\CoDeveloper3\StageMaster\bin;C:\Impulse\CoDeveloper3\MinGW\bin;C:\Impulse\CoDeveloper3\MinGW\lib\gcc-lib\mingw32\3.3.1;C:\Cadence\SPB_16.5\tools\pcb\bin;C:\Cadence\SPB_16.5\tools\bin;C:\Cadence\SPB_16.5\tools\libutil\bin;C:\Cadence\SPB_16.5\tools\fet\bin;C:\Cadence\SPB_16.5\tools\specctra\bin;C:\Cadence\SPB_16.5\tools\PSpice;C:\Cadence\SPB_16.5\tools\PSpice\Library;C:\Cadence\SPB_16.5\tools\Capture;C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:\Program Files\MATLAB\R2011a\runtime\win32;C:\Program Files\MATLAB\R2011a\bin;C:\Aldec\Active-HDL 9.2\bin;C:\PROGRA~1\Motorola\DSP\dsp\bin C:\Xilinx\14.2\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.2\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.2\ISE_DS\ISE\bin\nt;C:\Xilinx\14.2\ISE_DS\ISE\lib\nt;C:\Xilinx\Vivado\2012.2\bin;C:\Xilinx\14.2\ISE_DS\PlanAhead\bin;C:\Xilinx\14.2\ISE_DS\EDK\bin\nt;C:\Xilinx\14.2\ISE_DS\EDK\lib\nt;C:\Xilinx\14.2\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.2\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.2\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.2\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.2\ISE_DS\common\bin\nt;C:\Xilinx\14.2\ISE_DS\common\lib\nt;C:\Program Files\Common Files\Intel\Shared Files\cpp\bin\ia32;C:\Python27\;C:\Python27\Scripts;C:\WINDOWS\system32;C:\WINDOWS;C:\WINDOWS\System32\Wbem;C:\Program Files\Aldec\Active-HDL 8.2\BIN;C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;C:\Aldec\Active-HDL 8.3\BIN;C:\Impulse\CoDeveloper3\bin;C:\Impulse\CoDeveloper3\Libraries;C:\Impulse\CoDeveloper3\StageMaster\bin;C:\Impulse\CoDeveloper3\MinGW\bin;C:\Impulse\CoDeveloper3\MinGW\lib\gcc-lib\mingw32\3.3.1;C:\Cadence\SPB_16.5\tools\pcb\bin;C:\Cadence\SPB_16.5\tools\bin;C:\Cadence\SPB_16.5\tools\libutil\bin;C:\Cadence\SPB_16.5\tools\fet\bin;C:\Cadence\SPB_16.5\tools\specctra\bin;C:\Cadence\SPB_16.5\tools\PSpice;C:\Cadence\SPB_16.5\tools\PSpice\Library;C:\Cadence\SPB_16.5\tools\Capture;C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:\Program Files\MATLAB\R2011a\runtime\win32;C:\Program Files\MATLAB\R2011a\bin;C:\Aldec\Active-HDL 9.2\bin;C:\PROGRA~1\Motorola\DSP\dsp\bin C:\Xilinx\14.2\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.2\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.2\ISE_DS\ISE\bin\nt;C:\Xilinx\14.2\ISE_DS\ISE\lib\nt;C:\Xilinx\Vivado\2012.2\bin;C:\Xilinx\14.2\ISE_DS\PlanAhead\bin;C:\Xilinx\14.2\ISE_DS\EDK\bin\nt;C:\Xilinx\14.2\ISE_DS\EDK\lib\nt;C:\Xilinx\14.2\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.2\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.2\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.2\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.2\ISE_DS\common\bin\nt;C:\Xilinx\14.2\ISE_DS\common\lib\nt;C:\Program Files\Common Files\Intel\Shared Files\cpp\bin\ia32;C:\Python27\;C:\Python27\Scripts;C:\WINDOWS\system32;C:\WINDOWS;C:\WINDOWS\System32\Wbem;C:\Program Files\Aldec\Active-HDL 8.2\BIN;C:\Program Files\Microsoft SQL Server\100\Tools\Binn\;C:\Program Files\Microsoft SQL Server\100\DTS\Binn\;C:\Aldec\Active-HDL 8.3\BIN;C:\Impulse\CoDeveloper3\bin;C:\Impulse\CoDeveloper3\Libraries;C:\Impulse\CoDeveloper3\StageMaster\bin;C:\Impulse\CoDeveloper3\MinGW\bin;C:\Impulse\CoDeveloper3\MinGW\lib\gcc-lib\mingw32\3.3.1;C:\Cadence\SPB_16.5\tools\pcb\bin;C:\Cadence\SPB_16.5\tools\bin;C:\Cadence\SPB_16.5\tools\libutil\bin;C:\Cadence\SPB_16.5\tools\fet\bin;C:\Cadence\SPB_16.5\tools\specctra\bin;C:\Cadence\SPB_16.5\tools\PSpice;C:\Cadence\SPB_16.5\tools\PSpice\Library;C:\Cadence\SPB_16.5\tools\Capture;C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:\Program Files\MATLAB\R2011a\runtime\win32;C:\Program Files\MATLAB\R2011a\bin;C:\Aldec\Active-HDL 9.2\bin;C:\PROGRA~1\Motorola\DSP\dsp\bin XILINX C:\Xilinx\14.2\ISE_DS\ISE\ C:\Xilinx\14.2\ISE_DS\ISE\ C:\Xilinx\14.2\ISE_DS\ISE\ C:\Xilinx\14.2\ISE_DS\ISE\ XILINXD_LICENSE_FILE [e-mail] [e-mail] [e-mail] [e-mail] XILINX_DSP C:\Xilinx\14.2\ISE_DS\ISE C:\Xilinx\14.2\ISE_DS\ISE C:\Xilinx\14.2\ISE_DS\ISE C:\Xilinx\14.2\ISE_DS\ISE XILINX_EDK C:\Xilinx\14.2\ISE_DS\EDK C:\Xilinx\14.2\ISE_DS\EDK C:\Xilinx\14.2\ISE_DS\EDK C:\Xilinx\14.2\ISE_DS\EDK XILINX_PLANAHEAD C:\Xilinx\14.2\ISE_DS\PlanAhead C:\Xilinx\14.2\ISE_DS\PlanAhead C:\Xilinx\14.2\ISE_DS\PlanAhead C:\Xilinx\14.2\ISE_DS\PlanAhead XILINX_VIVADO C:\Xilinx\Vivado\2012.2 C:\Xilinx\Vivado\2012.2 C:\Xilinx\Vivado\2012.2 C:\Xilinx\Vivado\2012.2 XIL_MAP_LOCWARN 1 <  not set  > <  not set  > <  not set  >   Synthesis Property Settings Switch Name Property Name Value Default Value -ifn   seven_seg_bright_control.prj   -ofn   seven_seg_bright_control   -ofmt   NGC NGC -p   xc6slx16-3-csg324   -top   seven_seg_bright_control   -opt_mode Optimization Goal Speed Speed -opt_level Optimization Effort 1 1 -power Power Reduction NO No -iuc Use synthesis Constraints File NO No -keep_hierarchy Keep Hierarchy No No -netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized -rtlview Generate RTL Schematic Yes No -glob_opt Global Optimization Goal AllClockNets AllClockNets -read_cores Read Cores YES Yes -write_timing_constraints Write Timing Constraints NO No -cross_clock_analysis Cross Clock Analysis NO No -bus_delimiter Bus Delimiter <> <> -slice_utilization_ratio Slice Utilization Ratio 100 100 -bram_utilization_ratio BRAM Utilization Ratio 100 100 -dsp_utilization_ratio DSP Utilization Ratio 100 100 -reduce_control_sets   Auto Auto -fsm_extract   YES Yes -fsm_encoding   Auto Auto -safe_implementation   No No -fsm_style   LUT LUT -ram_extract   Yes Yes -ram_style   Auto Auto -rom_extract   Yes Yes -shreg_extract   YES Yes -rom_style   Auto Auto -auto_bram_packing   NO No -resource_sharing   YES Yes -async_to_sync   NO No -use_dsp48   Auto Auto -iobuf   YES Yes -max_fanout   100000 100000 -bufg   16 16 -register_duplication   YES Yes -register_balancing   No No -optimize_primitives   NO No -use_clock_enable   Auto Auto -use_sync_set   Auto Auto -use_sync_reset   Auto Auto -iob   Auto Auto -equivalent_register_removal   YES Yes -slice_utilization_ratio_maxmargin   5 0   Translation Property Settings Switch Name Property Name Value Default Value -intstyle   ise None -dd   _ngo None -p   xc6slx16-csg324-3 None -uc   Nexys3_Small.ucf None   Map Property Settings Switch Name Property Name Value Default Value -ol Place & Route Effort Level (Overall) high high -xt Extra Cost Tables 0 0 -ir Use RLOC Constraints OFF OFF -t Starting Placer Cost Table (1-100) Map 1 0 -r Register Ordering 4 4 -intstyle   ise None -lc LUT Combining off off -o   seven_seg_bright_control_map.ncd None -w   true false -pr Pack I/O Registers/Latches into IOBs off off -p   xc6slx16-csg324-3 None   Place and Route Property Settings Switch Name Property Name Value Default Value -intstyle   ise   -mt Enable Multi-Threading off off -ol Place & Route Effort Level (Overall) high std -w   true false   Operating System Information Operating System Information xst ngdbuild map par CPU Architecture/Speed Intel(R) Core(TM)2 Duo CPU E7500 @ 2.93GHz/2930 MHz Intel(R) Core(TM)2 Duo CPU E7500 @ 2.93GHz/2930 MHz Intel(R) Core(TM)2 Duo CPU E7500 @ 2.93GHz/2930 MHz Intel(R) Core(TM)2 Duo CPU E7500 @ 2.93GHz/2930 MHz Host pldlab7 pldlab7 pldlab7 pldlab7 OS Name Microsoft Windows XP Professional Microsoft Windows XP Professional Microsoft Windows XP Professional Microsoft Windows XP Professional OS Release Dodatek Service Pack 3 (build 2600) Dodatek Service Pack 3 (build 2600) Dodatek Service Pack 3 (build 2600) Dodatek Service Pack 3 (build 2600)