Xilinx Design Summary seven_seg_bright_control Project Status Project File: seven_seg_bright_control.xise Parser Errors: No Errors Module Name: seven_seg_bright_control Implementation State: New Target Device: xc6slx16-3csg324 Errors:   Product Version:ISE 14.2 Warnings:   Design Goal: Balanced Routing Results:   Design Strategy: Xilinx Default (unlocked) Timing Constraints:   Environment: System Settings Final Timing Score:      Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos Synthesis Report      Translation Report      Map Report      Place and Route Report      Power Report      Post-PAR Static Timing Report      Bitgen Report        Secondary Reports [-] Report NameStatusGenerated WebTalk ReportCurrentŚr 29. maj 09:58:02 2013 WebTalk Log FileCurrentŚr 29. maj 09:58:08 2013 Date Generated: 06/12/2013 - 08:07:20