LIS2L02AS
INERTIAL SENSOR:
2Axis - 2g/6g LINEAR ACCELEROMETER
PRODUCT PREVIEW
3V TO 5.25V SINGLE SUPPLY OPERATION
THE SENSITIVITY IS ADJUSTED WITH A
TOTAL ACCURACY OF ą10%
THE OUTPUT VOLTAGE, OFFSET,
SENSITIVITY AND TEST VOLTAGE ARE
RATIOMETRIC TO THE SUPPLY VOLTAGE
SO-24
ORDERING NUMBER: LIS2L02AS
DEVICE SENSITIVITY IS ON-CHIP FACTORY
TRIMMED
EMBEDDED SELF TEST
HIGH SHOCK SURVIVABILITY
a maximum bandwidth of 4.0 KHz for both the X and
Y axis. The device bandwidth may be reduced by us-
DESCRIPTION
ing external capacitances. A self-test capability al-
lows the user to check the functioning of the system.
The LIS2L02AS is a dual-axis linear accelerometer
that includes a sensing element and an IC interface
The LIS2L02AS is available in plastic SMD package
able to take the information from the sensing element
and it is specified over a temperature range extend-
and to provide an analog signal to the external world.
ing from -40�C to +85�C.
The sensing element, capable to detect the acceler-
The LIS2L02AS belongs to a family of products suit-
ation, is manufactured using a dedicated process
able for a variety of applications:
called THELMA (Thick Epi-Poly Layer for Microactu-
 Antitheft systems
ators and Accelerometers) developed by ST to pro-
 Inertial navigation
duce inertial sensors and actuators in silicon.
 Virtual reality input devices
The IC interface instead is manufactured using a
CMOS process that allows high level of integration to
 Vibration Monitoring, recording and compen-
design a dedicated circuit which is trimmed to better
sation
match the sensing element characteristics.
 Appliance control
The LIS2L02AS has a user selectable full scale of 2g,
 Robotics
6g and it is capable of measuring accelerations over
BLOCK DIAGRAM
Routx
Voutx
CHARGE S/H
S1X
AMPLIFIER
S1Y
rot
MUX DEMUX
S2Y
S2X
Routy
Vouty
S/H
CLOCK
TRIMMING CIRCUIT
VOLTAGE & CURRENT
& &
REFERENCE
TEST INTERFACE PHASE GENERATOR
December 2002 1/6
This is preliminary information on a new product now in development. Details are subject to change without notice.
LIS2L02AS
PIN DESCRIPTION
N� Pin Function
1 to 6 NC Internally not connected
7 Reserved Leave unconnected or connect to ground
8 Reserved Leave unconnected or connect to Vdd
9 Reserved Connect to Vdd or ground
10-11 Reserved Leave unconnected or connect to Vdd
12 FS Full Scale selection (Logic 0: 2g Full-scale; Logic 1: 6g Full-scale)
13 NC Internally not connected
14 PD Power Down (Logic 0: normal mode; Logic 1: Power-Down mode)
15 Voutx Output Voltage
16 ST Self Test (Logic 0: normal mode; Logic 1: Self-test)
17 Vouty Output Voltage
18 Vdd Power supply
19 GND 0V supply
20 to 24 NC Internally not connected
PIN CONNECTION (Top view)
NC NC
X
NC
NC
1 Y
NC
NC
NC
NC
NC
NC
NC GND
13
Reserved Vdd
DIRECTION OF THE
Reserved Vouty
DETECTABLE
ACCELERATIONS
Reserved ST
Reserved Voutx
Reserved PD
FS NC
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LIS2L02AS
ELECTRICAL CHARACTERISTCS (Temperature range -40�C to +85�C)
Symbol Parameter Test Condition Min. Typ. Max. Unit
Vdd Supply voltage 3 5.25 V
Idd Supply current 1.0 mA
Voff Zero-g level Tamb = 25�C Vdd/2-10% Vdd/2 Vdd/2+10% V
ratiometric to Vdd
Ar Acceleration range 0V on FS pin ą1.8 ą2.0 ą2.2 g
Vdd on FS pin ąą6.0 g
So Sensitivity ratiometric to Tamb = 25�C Vdd/5 10% Vdd/5 Vdd/5+10% V/g
Vdd
Full-scale = 2g
Tamb = 25�C Vdd/15 10% Vdd/15 Vdd/15+10% V/g
Full-scale = 6g
NL Non Linearity Best fit straight line ą0.3 %
X, Y axis
Full-scale = 2g
fuc Sensing Element Resonant X, Y axis 4.0 KHz
Frequency
an Acceleration noise density Vdd = 5V 50
�g/ Hz
Full-scale = 2g
Vt Self test output voltage Tamb = 25�C 100 mV
Ratiometric to Vdd
@ 5V
Vst Self test input Logic 0 level 0 0.8 V
Logic 1 level 2.8 Vdd V
Rout Output impedance 100 k&!
Cload Capacitive load drive 320 pF
1 FUNCTIONALITY
1.1 Sensing element
The THELMA process is utilized to create a surface micro-machined accelerometer. The technology allows to
carry out suspended silicon structures which are attached to the substrate in a few points called anchors and
free to move on a plane parallel to the substrate itself. To be compatible with the traditional packaging tech-
niques a cap is placed on top of the sensing element to avoid blocking the moving parts during the molding
phase.
The equivalent circuit for the sensing element is shown in the below figure; when a linear acceleration is applied,
the proof mass displaces from its nominal position, causing an imbalance in the capacitive half-bridge. This im-
balance is measured using charge integration in response to a voltage pulse applied to the sense capacitor.
The nominal value of the capacitors, at steady state, is few pF and when an acceleration is applied the maximum
variation of the capacitive load is few tenth of pF.
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LIS2L02AS
Figure 1. Equivalent electrical circuit
Cps1 Rs1
S1x
Cs1x
Cpr Rr
Cs2x
S2x
Cps2 Rs2
rot
Cps1 Rs1
S1y
Cs1y
Cpr Rr
Cs2y
S2y
Cps2 Rs2
1.2 IC Interface
The complete signal processing uses a fully differential structure, while the final stage converts the differential
signal into a single-ended one to be compatible with the external world.
The first stage is a low-noise capacitive amplifier that implements a Correlated Double Sampling (CDS) at its
output to cancel the offset and the 1/f noise. The produced signal is then sent to two different S&Hs, one for
each channel, and made available to the outside.
The low noise input amplifier operates at 200 kHz while the two S&Hs operate at a sampling frequency of 66
kHz. This allows a large oversampling ratio, which leads to in-band noise reduction and to an accurate output
waveform.
All the analog parameters (output offset voltage and sensitivity) are ratiometric to the voltage supply. Increasing
or decreasing the voltage supply, the sensitivity and the offset will increase or decrease linearly. The feature
provides the cancellation of the error related to the voltage supply along an analog to digital conversion chain.
1.3 Factory calibration
The IC interface is factory calibrated to provide to the final user a device ready to operate. The parameters which
are trimmed are: gain, offset, common mode and internal clock frequency.
The trimming values are stored inside the device by a poly-fuse structure. Any time the device is turned on, the
memorized bits are downloaded into the registers to be employed during the normal operation. The poly-fuse
approach allows the final user to utilize the device without any need for further calibration
4/6
LIS2L02AS
mm inch
DIM.
OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX.
MECHANICAL DATA
A 2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B 0.33 0.51 0.013 0.200
Weight: 0.60gr
C 0.23 0.32 0.009 0.013
15.60 0.598 0.614
D (1) 15.20
E 7.40 7.60 0.291 0.299
e 1.27 0.050
H 10.0 10.65 0.394 0.419
h 0.25 0;75 0.010 0.030
L 0.40 1.27 0.016 0.050
k 0� (min.), 8� (max.)
ddd 0.10 0.004
SO24
(1)  D dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
0070769 C
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LIS2L02AS
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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