a
DSP Microcomputer
ADSP-2189M
FEATURES FUNCTIONAL BLOCK DIAGRAM
PERFORMANCE
POWER-DOWN
CONTROL
13.3 ns Instruction Cycle Time @ 2.5 Volts (Internal),
FULL MEMORY
75 MIPS Sustained Performance MEMORY MODE
PROGRAMMABLE
DATA ADDRESS
PROGRAM DATA
I/O
Single-Cycle Instruction Execution GENERATORS PROGRAM EXTERNAL
MEMORY MEMORY
AND
SEQUENCER ADDRESS
32K 48K
FLAGS
DAG 1 DAG 2 BUS
Single-Cycle Context Switch
24 BIT 16 BIT
3-Bus Architecture Allows Dual Operand Fetches in EXTERNAL
DATA
PROGRAM MEMORY ADDRESS
BUS
Every Instruction Cycle
DATA MEMORY ADDRESS
BYTE DMA
Multifunction Instructions
CONTROLLER
PROGRAM MEMORY DATA
Power-Down Mode Featuring Low CMOS Standby
OR
Power Dissipation with 200 CLKIN Cycle Recovery DATA MEMORY DATA
EXTERNAL
from Power-Down Condition DATA
BUS
Low Power Dissipation in Idle Mode ARITHMETIC UNITS SERIAL PORTS TIMER
INTERNAL
ALU MAC SHIFTER SPORT 0 SPORT 1
DMA
PORT
INTEGRATION
ADSP-2100 BASE
HOST MODE
ADSP-2100 Family Code Compatible (Easy to Use Alge-
ARCHITECTURE
braic Syntax), with Instruction Set Extensions
192K Bytes of On-Chip RAM, Configured as 32K Words
Six External Interrupts
On-Chip Program Memory RAM and 48K Words On-
13 Programmable Flag Pins Provide Flexible System
Chip Data Memory RAM
Signaling
Dual Purpose Program Memory for Both Instruction
UART Emulation through Software SPORT Reconfiguration
and Data Storage
ICE-Port"! Emulator Interface Supports Debugging in
Independent ALU, Multiplier/Accumulator and Barrel
Final Systems
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
GENERAL DESCRIPTION
Programmable 16-Bit Interval Timer with Prescaler
The ADSP-2189M is a single-chip microcomputer optimized
100-Lead LQFP
for digital signal processing (DSP) and other high speed nu-
meric processing applications.
SYSTEM INTERFACE
Flexible I/O Structure Allows 2.5 V or 3.3 V Operation;
The ADSP-2189M combines the ADSP-2100 family base archi-
All Inputs Tolerate Up to 3.6 V, Regardless of Mode
tecture (three computational units, data address generators and
16-Bit Internal DMA Port for High Speed Access to On-
a program sequencer) with two serial ports, a 16-bit internal
Chip Memory (Mode Selectable)
DMA port, a byte DMA port, a programmable timer, Flag I/O,
4 MByte Memory Interface for Storage of Data Tables
extensive interrupt capabilities, and on-chip program and data
and Program Overlays (Mode Selectable)
memory.
8-Bit DMA to Byte Memory for Transparent Program
The ADSP-2189M integrates 192K bytes of on-chip memory
and Data Memory Transfers (Mode Selectable)
configured as 32K words (24-bit) of program RAM and 48K
I/O Memory Interface with 2048 Locations Supports
words (16-bit) of data RAM. Power-down circuitry is also pro-
Parallel Peripherals (Mode Selectable)
vided to meet the low power needs of battery operated portable
Programmable Memory Strobe and Separate I/O
equipment. The ADSP-2189M is available in a 100-lead LQFP
Memory Space Permits  Glueless System Design
package.
Programmable Wait-State Generation
In addition, the ADSP-2189M supports new instructions, which
Two Double-Buffered Serial Ports with Companding
include bit manipulations bit set, bit clear, bit toggle, bit test
Hardware and Automatic Data Buffering
new ALU constants, new multiplication instruction (x squared),
Automatic Booting of On-Chip Program Memory from
biased rounding, result free ALU operations, I/O memory trans-
Byte-Wide External Memory, e.g., EPROM, or
fers and global interrupt masking, for increased flexibility.
Through Internal DMA Port
ICE-Port is a trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or Tel: [phone] World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices.
Fax: [phone] © Analog Devices, Inc., 2000
ADSP-2189M
The EZ-ICE performs a full range of functions, including:
Fabricated in a high speed, low power, CMOS process, the
ADSP-2189M operates with a 13.3 ns instruction cycle time.
" In-target operation
Every instruction can execute in a single processor cycle.
" Up to 20 breakpoints
" Single-step or full-speed operation
The ADSP-2189M s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera- " Registers and memory values can be examined and altered
" PC upload and download functions
tions in parallel. In one processor cycle, the ADSP-2189M can:
" Instruction-level emulation of program booting and execution
" Generate the next program address
" Complete assembly and disassembly of instructions
" Fetch the next instruction
" C source-level debugging
" Perform one or two data moves
See  Designing An EZ-ICE-Compatible Target System in the
" Update one or two data address pointers
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as
" Perform a computational operation
well as the Designing an EZ-ICE compatible System section of
This takes place while the processor continues to:
this data sheet for the exact specifications of the EZ-ICE target
" Receive and transmit data through the two serial ports
board connector.
" Receive and/or transmit data through the internal DMA port
Additional Information
" Receive and/or transmit data through the byte DMA port
This data sheet provides a general overview of ADSP-2189M
" Decrement timer
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
DEVELOPMENT SYSTEM
User s Manual, Third Edition. For more information about the
The ADSP-2100 Family Development Software, a complete set
development tools, refer to the ADSP-2100 Family Develop-
of tools for software and hardware system development, sup-
ment Tools Data Sheet.
ports the ADSP-2189M. The System Builder provides a high
level method for defining the architecture of systems under
ARCHITECTURE OVERVIEW
development. The Assembler has an algebraic syntax that is easy
The ADSP-2189M instruction set provides flexible data moves
to program and debug. The Linker combines object files into an
and multifunction (one or two data moves with a computation)
executable file. The Simulator provides an interactive instruc-
instructions. Every instruction can be executed in a single pro-
tion-level simulation with a reconfigurable user interface to
cessor cycle. The ADSP-2189M assembly language uses an
display different portions of the hardware environment.
algebraic syntax for ease of coding and readability. A compre-
A PROM Splitter generates PROM programmer compatible
hensive set of development tools supports program development.
files. The C Compiler, based on the Free Software Foundation s
POWER-DOWN
GNU C Compiler, generates ADSP-2189M assembly source
CONTROL
FULL MEMORY
code. The source code debugger allows programs to be cor-
MEMORY MODE
PROGRAMMABLE
DATA ADDRESS
rected in the C environment. The Runtime Library includes over PROGRAM DATA
I/O
GENERATORS PROGRAM EXTERNAL
MEMORY MEMORY
AND
SEQUENCER ADDRESS
32K 48K
100 ANSI-standard mathematical and DSP-specific functions. FLAGS
DAG 1 DAG 2 BUS
24 BIT 16 BIT
EXTERNAL
The EZ-KIT Lite is a hardware/software kit offering a complete
DATA
PROGRAM MEMORY ADDRESS
BUS
development environment for the entire ADSP-21xx family: an
DATA MEMORY ADDRESS
BYTE DMA
ADSP-218x-based evaluation board with PC monitor software
CONTROLLER
PROGRAM MEMORY DATA
plus Assembler, Linker, Simulator and PROM Splitter software.
OR
DATA MEMORY DATA
The ADSP-218x EZ-KIT Lite is a low cost, easy to use hard-
EXTERNAL
DATA
ware platform on which you can quickly get started with your
BUS
ARITHMETIC UNITS SERIAL PORTS TIMER
DSP software design. The EZ-KIT Lite includes the following
INTERNAL
ALU MAC SHIFTER SPORT 0 SPORT 1
DMA
features:
PORT
ADSP-2100 BASE
HOST MODE
" 33 MHz ADSP-218x
ARCHITECTURE
" Full 16-bit Stereo Audio I/O with AD1847 SoundPort®
Figure 1. Functional Block Diagram
Codec
" RS-232 Interface to PC with Windows 3.1 Control Software
Figure 1 is an overall block diagram of the ADSP-2189M. The
" EZ-ICE Connector for Emulator Control
processor contains three independent computational units: the
" DSP Demo Programs
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
The ADSP-218x EZ-ICE® Emulator aids in the hardware de-
sions to support multiprecision computations. The ALU per-
bugging of an ADSP-2189M system. The emulator consists of
forms a standard set of arithmetic and logic operations; division
hardware, host computer resident software and the target board
primitives are also supported. The MAC performs single-cycle
connector. The ADSP-2189M integrates on-chip emulation
multiply, multiply/add and multiply/subtract operations with 40
support with a 14-pin ICE-Port interface. This interface pro-
bits of accumulation. The shifter performs logical and arith-
vides a simpler target board connection that requires fewer
metic shifts, normalization, denormalization and derive expo-
mechanical clearance considerations than other ADSP-2100
nent operations.
Family EZ-ICEs. The ADSP-2189M device need not be re-
moved from the target system when using the EZ-ICE, nor are
The shifter can be used to efficiently implement numeric
any adapters needed. Due to the small footprint of the EZ-ICE
format control including multiword and block floating-point
connector, emulation can be supported in final board designs.
representations.
EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.
 2 REV. A
ADSP-2189M
The internal result (R) bus connects the computational units so RESET signal. The two serial ports provide a complete synchro-
that the output of any unit may be the input of any unit on the nous serial interface with optional companding in hardware and
next cycle. a wide variety of framed or frameless data transmit and receive
modes of operation.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu- Each port can generate an internal programmable serial clock or
tational units. The sequencer supports conditional jumps, sub- accept an external serial clock.
routine calls and returns in a single cycle. With internal loop
The ADSP-2189M provides up to 13 general-purpose flag pins.
counters and loop stacks, the ADSP-2189M executes looped
The data input and output pins on SPORT1 can be alternatively
code with zero overhead; no explicit jump instructions are re-
configured as an input flag and an output flag. In addition, eight
quired to maintain loops.
flags are programmable as inputs or outputs and three flags are
Two data address generators (DAGs) provide addresses for always outputs.
simultaneous dual operand fetches (from data memory and
A programmable interval timer generates periodic interrupts. A
program memory). Each DAG maintains and updates four
16-bit count register (TCOUNT) decrements every n processor
address pointers. Whenever the pointer is used to access data
cycles, where n is a scaling value stored in an 8-bit register
(indirect addressing), it is post-modified by the value of one of
(TSCALE). When the value of the count register reaches zero,
four possible modify registers. A length value may be associated
an interrupt is generated and the count register is reloaded from
with each pointer to implement automatic modulo addressing
a 16-bit period register (TPERIOD).
for circular buffers.
Serial Ports
Efficient data transfer is achieved with the use of five internal
The ADSP-2189M incorporates two complete synchronous
buses:
serial ports (SPORT0 and SPORT1) for serial communications
" Program Memory Address (PMA) Bus and multiprocessor communication.
" Program Memory Data (PMD) Bus
Here is a brief list of the capabilities of the ADSP-2189M
" Data Memory Address (DMA) Bus
SPORTs. For additional information on Serial Ports, refer to
" Data Memory Data (DMD) Bus
the ADSP-2100 Family User s Manual, Third Edition.
" Result (R) Bus
" SPORTs are bidirectional and have a separate, double-buff-
The two address buses (PMA and DMA) share a single external
ered transmit and receive section.
address bus, allowing memory to be expanded off-chip and the
" SPORTs can use an external serial clock or generate their
two data buses (PMD and DMD) share a single external data
own serial clock internally.
bus. Byte memory space and I/O memory space also share the
external buses. " SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
Program memory can store both instructions and data, permit-
synchronization signals internally or externally generated.
ting the ADSP-2189M to fetch two operands in a single cycle,
Frame sync signals are active high or inverted, with either of
one from program memory and one from data memory. The
two pulsewidths and timings.
ADSP-2189M can fetch an operand from program memory and
the next instruction in the same cycle. " SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
In lieu of the address and data bus for external memory connec-
to CCITT recommendation G.711.
tion, the ADSP-2189M may be configured for 16-bit Internal
DMA port (IDMA port) connection to external systems. The " SPORT receive and transmit sections can generate unique
IDMA port is made up of 16 data/address pins and five control interrupts on completing a data word transfer.
pins. The IDMA port provides transparent, direct access to the
" SPORTs can receive and transmit an entire circular buffer of
DSPs on-chip program and data RAM.
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
" SPORT0 has a multichannel interface to selectively receive
and can directly address up to four megabytes of external RAM
and transmit a 24- or 32-word, time-division multiplexed,
or ROM for off-chip storage of program overlays or data tables.
serial bitstream.
The byte memory and I/O memory space interface supports
" SPORT1 can be configured to have two external interrupts
slow memories and I/O memory-mapped peripherals with pro-
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
grammable wait-state generation. External devices can gain
internally generated serial clock may still be used in this con-
control of external buses with bus request/grant signals (BR,
figuration.
BGH and BG). One execution mode (Go Mode) allows the
ADSP-2189M to continue running from on-chip memory.
PIN DESCRIPTIONS
Normal execution mode requires the processor to halt while
The ADSP-2189M will be available in a 100-lead LQFP pack-
buses are granted.
age. In order to maintain maximum functionality and reduce
package size and pin count, some serial port, programmable
The ADSP-2189M can respond to eleven interrupts. There can
flag, interrupt and external bus pins have dual, multiplexed
be up to six external interrupts (one edge-sensitive, two level-
functionality. The external bus pins are configured during
sensitive and three configurable) and seven internal interrupts
RESET only, while serial port pins are software configurable
generated by the timer, the serial ports (SPORTs), the Byte
during program execution. Flag and interrupt functionality is
DMA port and the power-down circuitry. There is also a master
retained concurrently on multiplexed pins. In cases where pin
REV. A
 3
ADSP-2189M
NOTES
functionality is reconfigurable, the default state is shown in plain
1
Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to
text; alternate functionality is shown in italics.
enable the corresponding interrupts, then the DSP will vector to the appropri-
Common-Mode Pins ate interrupt vector address when the pin is asserted, either by external devices,
or set as a programmable flag.
Pin # of 2
SPORT configuration determined by the DSP System Control Register. Soft-
Name(s) Pins I/O Function
ware configurable.
Memory Interface Pins
RESET 1 I Processor Reset Input
The ADSP-2189M processor can be used in one of two modes,
BR 1 I Bus Request Input
Full Memory Mode, which allows BDMA operation with full
BG 1 O Bus Grant Output
external overlay memory and I/O capability, or Host Mode,
BGH 1 O Bus Grant Hung Output
which allows IDMA operation with limited external addressing
DMS 1 O Data Memory Select Output
capabilities. The operating mode is determined by the state of
PMS 1 O Program Memory Select Output the Mode C pin during RESET and cannot be changed while
the processor is running.
IOMS 1 O Memory Select Output
BMS 1 O Byte Memory Select Output Full Memory Mode Pins (Mode C = 0)
CMS 1 O Combined Memory Select Output
Pin # of
RD 1 O Memory Read Enable Output Name Pins I/O Function
WR 1 O Memory Write Enable Output
A13:0 14 O Address Output Pins for Program,
IRQ2 1 I Edge- or Level-Sensitive Interrupt
Data, Byte and I/O Spaces
Requests1
D23:0 24 I/O Data I/O Pins for Program, Data,
PF7 I/O Programmable I/O Pin.
Byte and I/O Spaces (8 MSBs are
also used as Byte Memory addresses.)
IRQL1 1 I Level-Sensitive Interrupt Requests1
PF6 I/O Programmable I/O Pin
IRQL0 1 I Level-Sensitive Interrupt Requests1 Host Mode Pins (Mode C = 1)
Pin # of
PF5 I/O Programmable I/O Pin
IRQE 1 I Edge-Sensitive Interrupt Requests1 Name Pins I/O Function
PF4 I/O Programmable I/O Pin
IAD15:0 16 I/O IDMA Port Address/Data Bus
Mode D 1 I Mode Select Input Checked Only A0 1 O Address Pin for External I/O,
During RESET Program, Data, or Byte Access1
PF3 I/O Programmable I/O Pin During D23:8 16 I/O Data I/O Pins for Program, Data
Normal Operation Byte and I/O Spaces
IWR 1 I IDMA Write Enable
Mode C 1 I Mode Select Input Checked Only
IRD 1 I IDMA Read Enable
During RESET
IAL 1 I IDMA Address Latch Pin
PF2 I/O Programmable I/O Pin During
IS 1 I IDMA Select
Normal Operation
IACK 1 O IDMA Port Acknowledge Config-
Mode B 1 I Mode Select Input Checked
urable in Mode D; Open Drain
Only During RESET
PF1 I/O Programmable I/O Pin During NOTE
1
In Host Mode, external peripheral addresses can be decoded using the A0,
Normal Operation
CMS, PMS, DMS and IOMS signals.
Mode A 1 I Mode Select Input Checked Only
During RESET Interrupts
PF0 I/O Programmable I/O Pin During The interrupt controller allows the processor to respond to the
Normal Operation eleven possible interrupts and reset with minimum overhead.
The ADSP-2189M provides four dedicated external interrupt
CLKIN, XTAL 2 I Clock or Quartz Crystal Input
input pins, IRQ2, IRQL0, IRQL1 and IRQE (shared with the
CLKOUT 1 O Processor Clock Output
PF7:4 pins). In addition, SPORT1 may be reconfigured for
SPORT0 5 I/O Serial Port I/O Pins
IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six
SPORT1 5 I/O Serial Port I/O Pins
external interrupts. The ADSP-2189M also supports internal
IRQ1:0, FI, FO Edge- or Level-Sensitive Interrupts,
interrupts from the timer, the byte DMA port, the two serial
Flag In, Flag Out2
ports, software and the power-down control circuit. The inter-
PWD 1 I Power-Down Control Input
rupt levels are internally prioritized and individually maskable
(except power-down and reset). The IRQ2, IRQ0 and IRQ1
PWDACK 1 O Power-Down Control Output
input pins can be programmed to be either level- or edge-sensi-
FL0, FL1, FL2 3 O Output Flags
tive. IRQL0 and IRQL1 are level-sensitive and IRQE is edge-
VDDINT 2 I Internal VDD (2.5 V) Power
sensitive. The priorities and vector addresses of all interrupts are
VDDEXT 4 I External VDD (2.5 V or 3.3 V)
shown in Table I.
Power
GND 10 I Ground
EZ-Port 9 I/O For Emulation Use
 4 REV. A
ADSP-2189M
Table I. Interrupt Priority and Interrupt Vector Addresses Third Edition,  System Interface chapter, for detailed infor-
mation about the power-down feature.
Interrupt Vector
" Quick recovery from power-down. The processor begins
Source Of Interrupt Address (Hex)
executing instructions in as few as 200 CLKIN cycles.
RESET (or Power-Up with PUCR = 1) 0000 (Highest Priority)
" Support for an externally generated TTL or CMOS proces-
Power-Down (Nonmaskable) 002C
sor clock. The external clock can continue running during
IRQ2 0004
power-down without affecting the lowest power rating and
IRQL1 0008
200 CLKIN cycle recovery.
IRQL0 000C
" Support for crystal operation includes disabling the oscillator
SPORT0 Transmit 0010
to save power (the processor automatically waits approxi-
SPORT0 Receive 0014
mately 4096 CLKIN cycles for the crystal oscillator to start
IRQE 0018
or stabilize) and letting the oscillator run to allow 200 CLKIN
BDMA Interrupt 001C
cycle start up.
SPORT1 Transmit or IRQ1 0020
SPORT1 Receive or IRQ0 0024
" Power-down is initiated by either the power-down pin
Timer 0028 (Lowest Priority)
(PWD) or the software power-down force bit. Interrupt
support allows an unlimited number of instructions to be
Interrupt routines can either be nested with higher priority
executed before optionally powering down. The power-down
interrupts taking precedence or processed sequentially. Inter-
interrupt also can be used as a nonmaskable, edge-sensitive
rupts can be masked or unmasked with the IMASK register.
interrupt.
Individual interrupt requests are logically ANDed with the bits
" Context clear/save control allows the processor to continue
in IMASK; the highest priority unmasked interrupt is then
where it left off or start with a clean context when leaving the
selected. The power-down interrupt is nonmaskable.
power-down state.
The ADSP-2189M masks all interrupts for one instruction cycle
" The RESET pin also can be used to terminate power-down.
following the execution of an instruction that modifies the IMASK
register. This does not affect serial port autobuffering or DMA
" Power-down acknowledge pin indicates when the processor
transfers.
has entered power-down.
The interrupt control register, ICNTL, controls interrupt nest- Idle
ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
When the ADSP-2189M is in the Idle Mode, the processor
be either edge- or level-sensitive. The IRQE pin is an external
waits indefinitely in a low power state until an interrupt occurs.
edge-sensitive interrupt and can be forced and cleared. The
When an unmasked interrupt occurs, it is serviced; execution
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
then continues with the instruction following the IDLE instruc-
tion. In Idle mode IDMA, BDMA and autobuffer cycle steals
The IFC register is a write-only register used to force and clear
still occur.
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
Slow Idle
are twelve levels deep to allow interrupt, loop and subroutine
The IDLE instruction is enhanced on the ADSP-2189M to let
nesting. The following instructions allow global enable or dis- the processor s internal clock signal be slowed, further reducing
able servicing of the interrupts (including power-down), regard- power consumption. The reduced clock frequency, a program-
less of the state of IMASK. Disabling the interrupts does not mable fraction of the normal clock rate, is specified by a select-
able divisor given in the IDLE instruction.
affect serial port autobuffering or DMA.
The format of the instruction is:
ENA INTS;
DIS INTS;
IDLE (n);
When the processor is reset, interrupt servicing is enabled.
where n = 16, 32, 64 or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
LOW POWER OPERATION
it is in this state, the processor s other internal clock signals,
The ADSP-2189M has three low power modes that significantly
such as SCLK, CLKOUT and timer clock, are reduced by the
reduce the power dissipation when the device operates under
same ratio. The default form of the instruction, when no clock
standby conditions. These modes are:
divisor is given, is the standard IDLE instruction.
" Power-Down
When the IDLE (n) instruction is used, it effectively slows down
" Idle
the processor s internal clock and thus its response time to in-
" Slow Idle
coming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
The CLKOUT pin may also be disabled to reduce external
interrupt is received, the ADSP-2189M will remain in the idle
power dissipation.
state for up to a maximum of n processor cycles (n = 16, 32, 64,
Power-Down
or 128) before resuming normal operation.
The ADSP-2189M processor has a low power feature that lets
When the IDLE (n) instruction is used in systems that have an
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power- externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor s reduced internal clock rate.
down features. Refer to the ADSP-2100 Family User s Manual,
Under these conditions, interrupts must not be generated at a
REV. A
 5
ADSP-2189M
faster rate than can be serviced, due to the additional time the Clock Signals
processor takes to come out of the idle state (a maximum of n The ADSP-2189M can be clocked by either a crystal or a TTL-
processor cycles). compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
SYSTEM INTERFACE
or operated below the specified frequency during normal opera-
Figure 2 shows typical basic system configurations with the
tion. The only exception is while the processor is in the power-
ADSP-2189M, two serial devices, a byte-wide EPROM and
down state. For additional information, refer to Chapter 9,
optional external program and data overlay memories (mode
ADSP-2100 Family User s Manual, Third Edition for detailed
selectable). Programmable Wait-State generation allows the
information on this power-down feature.
processor connects easily to slow peripheral devices. The
If an external clock is used, it should be a TTL-compatible
ADSP-2189M also provides four external interrupts and two
signal running at half the instruction rate. The signal is con-
serial ports or six external interrupts and one serial port. Host
nected to the processor s CLKIN input. When an external clock
Memory Mode allows access to the full external data bus, but
is used, the XTAL input must be left unconnected.
limits addressing to a single address bit (A0). Additional system
peripherals can be added in this mode through the use of exter- The ADSP-2189M uses an input clock with a frequency equal
nal hardware to generate and latch address signals.
to half the instruction rate; a 37.50 MHz input clock yields a
13.3 ns processor cycle (which is equivalent to 75 MHz). Nor-
mally, instructions are executed in a single processor cycle. All
FULL MEMORY MODE
device timing is relative to the internal instruction clock rate,
ADSP-2189M
14 A13-0
1/2x CLOCK
ADDR13-0 which is indicated by the CLKOUT signal when enabled.
CLKIN
OR
D23-16 A0-A21
XTAL
CRYSTAL
Because the ADSP-2189M includes an on-chip oscillator cir-
BYTE
24 D15-8
FL0-2
MEMORY
DATA23-0 DATA
cuit, an external crystal may be used. The crystal should be
IRQ2/PF7
IRQE/PF4 connected across the CLKIN and XTAL pins, with two capaci-
BMS CS
IRQL0/PF5
tors connected as shown in Figure 3. Capacitor values are de-
IRQL1/PF6 A10-0
WR
ADDR
MODE D/PF3
pendent on crystal type and should be specified by the crystal
RD D23-8
I/O SPACE
MODE C/PF2
DATA
(PERIPHERALS)
MODE B/PF1 manufacturer. A parallel-resonant, fundamental frequency,
MODE A/PF0
2048 LOCATIONS
IOMS CS
microprocessor-grade crystal should be used.
SPORT1
A13-0
SCLK1
ADDR A clock output (CLKOUT) signal is generated by the processor
OVERLAY
RFS1 OR IRQ0
D23-0
SERIAL MEMORY
TFS1 OR IRQ1 at the processor s cycle rate. This can be enabled and disabled
DATA
DEVICE
TWO 8K
DT1 OR FO
PM SEGMENTS by the CLKODIS bit in the SPORT0 Autobuffer Control
DR1 OR FI
PMS
DMS
Register.
TWO 8K
CMS
SPORT0
DM SEGMENTS
SCLK0
BR
RFS0
BG
SERIAL
TFS0
BGH
DEVICE
DT0
PWD
DR0
XTAL
CLKIN CLKOUT
PWDACK
HOST MEMORY MODE
DSP
ADSP-2189M
1/2x CLOCK
CLKIN
1
OR
A0
XTAL
CRYSTAL
FL0-2
Figure 3. External Crystal Connections
16
IRQ2/PF7
IRQE/PF4 DATA23-8
Reset
IRQL0/PF5
IRQL1/PF6
BMS
The RESET signal initiates a master reset of the ADSP-2189M.
MODE D/PF3
WR The RESET signal must be asserted during the power-up se-
MODE C/PF2
MODE B/PF1
RD
quence to assure proper initialization. RESET during initial
MODE A/PF0
power-up must be held long enough to allow the internal clock
SPORT1
IOMS
SCLK1
to stabilize. If RESET is activated any time after power-up, the
RFS1 OR IRQ0
SERIAL
TFS1 OR IRQ1
clock continues to run and does not require stabilization time.
DEVICE
DT1 OR FO
DR1 OR FI
The power-up sequence is defined as the total time required for
SPORT0
PMS
SCLK0 the crystal oscillator circuit to stabilize after a valid VDD is ap-
DMS
RFS0
SERIAL CMS
plied to the processor and for the internal phase-locked loop
TFS0
DEVICE
DT0
BR
(PLL) to lock onto the specific crystal frequency. A minimum of
DR0
BG
BGH 2000 CLKIN cycles ensures that the PLL has locked but does
IDMA PORT
PWD
IRD/D6
not include the crystal oscillator start-up time. During this
SYSTEM PWDACK
IWR/D7
INTERFACE
IS/D4
power-up sequence the RESET signal should be held low. On
OR
IAL/D5
CONTROLLER
IACK/D3 any subsequent resets, the RESET signal must meet the mini-
16
IAD15-0
mum pulsewidth specification, tRSP.
The RESET input contains some hysteresis; however, if you use
Figure 2. ADSP-2189M Basic System Interface
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.
 6 REV. A
ADSP-2189M
Table II. ADSP-2189M Modes of Operation
MODE D MODE C MODE B MODE A Booting Method
X 0 0 0 BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Full Memory Mode.1
X010No automatic boot operations occur. Program execution starts at external
memory location 0. Chip is configured in Full Memory Mode. BDMA can
still be used but the processor does not automatically use or wait for these
operations.
0100BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Host Mode. IACK has active pull-down.
(REQUIRES ADDITIONAL HARDWARE).
0101IDMA feature is used to load any internal memory as desired. Program ex-
ecution is held off until internal program memory location 0 is written to.
Chip is configured in Host Mode. IACK has active pull-down.1
1100BDMA feature is used to load the first 32 program memory words from the
byte memory space. Program execution is held off until all 32 words have
been loaded. Chip is configured in Host Mode; IACK requires external pull-
down. (REQUIRES ADDITIONAL HARDWARE).
1101IDMA feature is used to load any internal memory as desired. Program ex-
ecution is held off until internal program memory location 0 is written to.
Chip is configured in Host Mode. IACK requires external pull-down.1
NOTE
1
Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
The master reset sets all internal stack pointers to the empty Passive Configuration involves the use a pull-up or pull-down
stack condition, masks all interrupts and clears the MSTAT resistor connected to the Mode C pin. To minimize power
register. When RESET is released, if there is no pending bus consumption, or if the PF2 pin is to be used as an output in the
request and the chip is configured for booting, the boot-loading DSP application, a weak pull-up or pull-down, on the order of
sequence is performed. The first instruction is fetched from 10 k&!, can be used. This value should be sufficient to pull the
on-chip program memory location 0x0000 once boot loading pin to the desired level and still allow the pin to operate as a
completes. programmable flag output without undue strain on the processor s
output driver. For minimum power consumption during power-
Power Supplies
down, reconfigure PF2 to be an input, as the pull-up or pull-
The ADSP-2189M has separate power supply connections for
down will hold the pin in a known state and will not switch.
the internal (VDDINT) and external (VDDEXT) power supplies.
The internal supply must meet the 2.5 V requirement. The Active Configuration involves the use of a three-statable ex-
external supply can be connected to either a 2.5 V or 3.3 V ternal driver connected to the Mode C pin. A driver s output
supply. All external supply pins must be connected to the same enable should be connected to the DSP s RESET signal such
supply. All input and I/O pins can tolerate input voltages up that it only drives the PF2 pin when RESET is active (low).
to 3.6 V regardless of the external supply voltage. This fea- When RESET is deasserted, the driver should three-state, thus
ture provides maximum flexibility in mixing 2.5 V and 3.3 V allowing full use of the PF2 pin as either an input or output. To
components. minimize power consumption during power-down, configure
the programmable flag as an output when connected to a three-
MODES OF OPERATION stated buffer. This ensures that the pin will be held at a constant
Setting Memory Mode level and will not oscillate should the three-state driver s level
Memory Mode selection for the ADSP-2189M is made during hover around the logic switching point.
chip reset through the use of the Mode C pin. This pin is multi-
IACK Configuration
plexed with the DSP s PF2 pin, so care must be taken in how
Mode D = 0 and in host mode: IACK is an active, driven signal
the mode selection is made. The two methods for selecting the
and cannot be wire OR-ed.
value of Mode C are active and passive.
REV. A
 7
ADSP-2189M
PM (MODE B = 0)
PM (MODE B = 1)1
ALWAYS
ACCESSIBLE RESERVED
AT ADDRESS
0 2000
0 0000  0 1FFF
0 3FFF
ACCESSIBLE WHEN
0 2000
PMOVLAY = 0
0 3FFF
ACCESSIBLE WHEN
0 2000
PMOVLAY = 0
INTERNAL
0 3FFF
RESERVED
MEMORY
0 2000 0 0000
INTERNAL ACCESSIBLE WHEN
0 3FFF RESERVED
0 1FFF2
MEMORY PMOVLAY = 4
0 2000
0 0000
ACCESSIBLE WHEN ACCESSIBLE WHEN
0 3FFF2
PMOVLAY = 5 PMOVLAY = 1 0 1FFF2
0 2000
ACCESSIBLE WHEN EXTERNAL
RESERVED
PMOVLAY = 1 0 3FFF2 MEMORY
EXTERNAL
ACCESSIBLE WHEN
MEMORY 1
WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0
PMOVLAY = 2
2
SEE TABLE III FOR PMOVLAY BITS
PROGRAM MEMORY PROGRAM MEMORY
MODE B = 0 MODE B = 1 ADDRESS
ADDRESS
0 3FFF 0 3FFF
8K INTERNAL
PMOVLAY = 0, 4, 5
8K INTERNAL
OR
PMOVLAY = 0
8K EXTERNAL
PMOVLAY = 1, 2
0 2000 0 2000
0 1FFF 0 1FFF
8K EXTERNAL
8K INTERNAL
0 0000 0 0000
Figure 4. Program Memory
Mode D = 1 and in host mode: IACK is an open source and Data Memory
requires an external pull-down, but multiple IACK pins can be Data Memory, Full Memory Mode is a 16-bit-wide space
wire OR-ed together. used for the storage of data variables and for memory-mapped
control registers. The ADSP-2189M has 48K words on Data
MEMORY ARCHITECTURE Memory RAM on-chip. Part of this space is used by 32 memory-
The ADSP-2189M provides a variety of memory and peripheral mapped registers. Support also exists for up to two 8K external
interface options. The key functional groups are Program Memory, memory overlay spaces through the external data bus. All inter-
Data Memory, Byte Memory and I/O. Refer to the following nal accesses complete in one cycle. Accesses to external memory
figures and tables for PM and DM memory allocations in the are timed using the wait-states specified by the DWAIT register
ADSP-2189M. and the wait-state mode bit.
Program Memory
DATA MEMORY ADDRESS
Program Memory, Full Memory Mode is a 24-bit-wide space DATA MEMORY
32 MEMORY 0 3FFF
MAPPED
for storing both instruction op codes and data. The ADSP-2189M
ALWAYS
0 3FE0
REGISTERS
ACCESSIBLE
has 32K words of Program Memory RAM on chip and the
0 3FDF
INTERNAL
AT ADDRESS
8160
0 2000  0 3FFF
capability of accessing up to two 8K external memory overlay
0 2000
WORDS
0 0000
0 1FFF
spaces using the external data bus.
0 1FFF
8K INTERNAL
ACCESSIBLE WHEN
DMOVLAY =
0 0000
DMOVLAY = 0
Program Memory, Host Mode allows access to all internal 0, 4, 5, 6, 7
0 1FFF
OR
memory. External overlay access is limited by a single external
0 0000 EXTERNAL 8K
ACCESSIBLE WHEN
DMOVLAY = 1, 2
0 1FFF
DMOVLAY = 4
0 0000
address line (A0). External program execution is not available in
0 0000
ACCESSIBLE WHEN
host mode due to a restricted data bus that is 16-bits wide only.
0 1FFF
DMOVLAY = 5
0 0000
INTERNAL ACCESSIBLE WHEN
MEMORY DMOVLAY = 6 0 1FFF
Table III. PMOVLAY Bits
0 0000
ACCESSIBLE WHEN
0 1FFF
DMOVLAY = 7
PMOVLAY Memory A13 A12:0
ACCESSIBLE WHEN
0 0000
DMOVLAY = 1
0 1FFF
0, 4, 5 Internal Not Applicable Not Applicable
EXTERNAL
ACCESSIBLE WHEN
MEMORY
1 External 0 13 LSBs of Address DMOVLAY = 2
Overlay 1 Between 0x2000
Figure 5. Data Memory Map
and 0x3FFF
2 External 1 13 LSBs of Address
Overlay 2 Between 0x2000
and 0x3FFF
 8 REV. A
ADSP-2189M
Data Memory, Host Mode allows access to all internal I/O Space (Full Memory Mode)
memory. External overlay access is limited by a single external The ADSP-2189M supports an additional external memory
address line (A0). space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
Table IV. DMOVLAY Bits registers) or to bus interface ASIC data registers. I/O space
supports 2048 locations of 16-bit-wide data. The lower eleven
PMOVLAY Memory A13 A12:0
bits of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
0, 4, 5, 6, 7 Internal Not Applicable Not Applicable
Family instruction set to read from and write to I/O memory
1 External 0 13 LSBs of Address
space. The I/O space also has four dedicated three-bit wait-state
Overlay 1 Between 0x2000
registers, IOWAIT0 3, which, in combination with the wait-
and 0x3FFF
state mode bit, specify up to 15 wait-states to be automatically
2 External 1 13 LSBs of Address
generated for each of four regions. The wait-states act on ad-
Overlay 2 Between 0x2000
dress ranges as shown in Table V.
and 0x3FFF
Table V. Wait-States
Memory Mapped Registers (New to the ADSP-2189M)
The ADSP-2189M has three memory mapped registers that
Address Range Wait-State Register
differ from other ADSP-21xx Family DSPs. The slight modifi-
cations to these registers (Wait-State Control, Programmable 0x000 0x1FF IOWAIT0 and Wait-State Mode Select Bit
Flag and Composite Select Control and System Control) pro- 0x200 0x3FF IOWAIT1 and Wait-State Mode Select Bit
vide the ADSP-2189M s wait-state and BMS control features. 0x400 0x5FF IOWAIT2 and Wait-State Mode Select Bit
0x600 0x7FF IOWAIT3 and Wait-State Mode Select Bit
WAIT-STATE CONTROL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Composite Memory Select (CMS)
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DM(0x3FFE)
The ADSP-2189M has a programmable memory select signal
that is useful for generating memory select signals for memories
DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAIT0
mapped to more than one space. The CMS signal is generated
WAIT STATE MODE SELECT (ADSP-2189M)
to have the same timing as each of the individual memory
0 = NORMAL MODE (DWAIT, IOWAIT0-3 = N WAIT STATES, RANGING FROM 0 TO 7)
select signals (PMS, DMS, BMS, IOMS) but can combine
1 = 2N+1 MODE (DWAIT, IOWAIT0-3 = N WAIT STATES, RANGING FROM 0 TO 15)
their functionality.
Figure 6. Wait-State Control Register (ADSP-2189M)
When set, each bit in the CMSSEL register causes the CMS
PROGRAMMABLE FLAG & COMPOSITE SELECT CONTROL signal to be asserted when the selected memory select is as-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
serted. For example, to use a 32K word memory to act as both
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 DM(0x3FE6)
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip select
BMWAIT CMSSEL PFTYPE
of the memory, and use either DMS or PMS as the additional
(BIT-15, ADSP-2189M) 0 = DISABLE CMS 0 = INPUT
1 = ENABLE CMS 1 = OUTPUT
address bit.
(WHERE BIT: 11-IOM, 10BM, 9-DM, 8-PM)
The CMS pin functions like the other memory select signals,
Figure 7. Programmable Flag and Composite Select Con-
with the same timing and bus request logic. A 1 in the enable bit
trol Register
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at
SYSTEM CONTROL
reset, except the BMS bit.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 DM(0x3FFF) Byte Memory Select (BMS)
The ADSP-2189M s BMS disable feature combined with the
RESERVED, ALWAYS = 0 PWAIT
CMS pin lets you use multiple memories in the byte memory
(ADSP-2189M) PROGRAM MEMORY
WAIT STATES
SPORT0 ENABLE
space. For example, an EPROM could be attached to the BMS
0 = DISABLE
select, and an SRAM could be connected to CMS. Because
1 = ENABLE
DISABLE BMS (ADSP-2189M)
0 = ENABLE BMS BMS is enabled at reset, the EPROM would be used for boot-
SPORT1 ENABLE
1 = DISABLE BMS, EXCEPT WHEN MEMORY
0 = DISABLE
ing. After booting, software could disable BMS and set the
STROBES ARE THREE-STATED
1 = ENABLE
CMS signal to respond to BMS, enabling the SRAM.
SPORT1 CONFIGURE
0 = FI, FO, IRQ0, IRQ1, SCLK
1 = SPORT1
Figure 8. System Control Register
REV. A
 9
ADSP-2189M
Byte Memory BDMA accesses can cross page boundaries during sequential
The byte memory space is a bidirectional, 8-bit-wide, external addressing. A BDMA interrupt is generated on the completion
memory space used to store programs and data. Byte memory is of the number of transfers specified by the BWCOUNT register.
accessed using the BDMA feature. The byte memory space
The BWCOUNT register is updated after each transfer so it can
consists of 256 pages, each of which is 16K × 8.
be used to check the status of the transfers. When it reaches
The byte memory space on the ADSP-2189M supports read zero, the transfers have finished and a BDMA interrupt is gener-
and write operations as well as four different data formats. The ated. The BMPAGE and BEAD registers must not be accessed
byte memory uses data bits 15:8 for data. The byte memory by the DSP during BDMA operations.
uses data bits 23:16 and address bits 13:0 to create a 22-bit
The source or destination of a BDMA transfer will always be
address. This allows up to a 4 meg × 8 (32 megabit) ROM or
on-chip program or data memory.
RAM to be used without glue logic. All byte memory accesses
When the BWCOUNT register is written with a nonzero value
are timed by the BMWAIT register and the wait-state mode bit.
the BDMA circuit starts executing byte memory accesses with
Byte Memory DMA (BDMA, Full Memory Mode)
wait-states set by BMWAIT. These accesses continue until the
The Byte memory DMA controller allows loading and storing of
count reaches zero. When enough accesses have occurred to
program instructions and data using the byte memory space.
create a destination word, it is transferred to or from on-chip
The BDMA circuit is able to access the byte memory space
memory. The transfer takes one DSP cycle. DSP accesses to
while the processor is operating normally and steals only one
external memory have priority over BDMA byte memory
DSP cycle per 8-, 16- or 24-bit word transferred.
accesses.
The BDMA Context Reset bit (BCR) controls whether the
BDMA CONTROL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
processor is held off while the BDMA accesses are occurring.
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 DM (0 3FE3)
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
BMPAGE BDMA BTYPE
OVERLAY
execution while the BDMA accesses are occurring, to clear the
BITS
BDIR
context of the processor, and start execution at address 0 when
0 = LOAD FROM BM
1 = STORE TO BM
the BDMA accesses have completed.
BCR
0 = RUN DURING BDMA
The BDMA overlay bits specify the OVLAY memory blocks to
1 = HALT DURING BDMA
be accessed for internal memory.
Figure 9. BDMA Control Register
The BMWAIT field, which has four bits on ADSP-2189M,
The BDMA circuit supports four different data formats which
allows selection of up to 15 wait-states for BDMA transfers.
are selected by the BTYPE register field. The appropriate num-
Internal Memory DMA Port (IDMA Port; Host Memory
ber of 8-bit accesses are done from the byte memory space to
Mode)
build the word size selected. Table VI shows the data formats
The IDMA Port provides an efficient means of communication
supported by the BDMA circuit.
between a host system and the ADSP-2189M. The port is used
to access the on-chip program memory and data memory of the
Table VI. Data Formats
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP s memory-
Internal
mapped control registers. A typical IDMA transfer process is
BTYPE Memory Space Word Size Alignment
described as follows:
00 Program Memory 24 Full Word
1. Host starts IDMA transfer.
01 Data Memory 16 Full Word
10 Data Memory 8 MSBs 2. Host checks IACK control line to see if the DSP is busy.
11 Data Memory 8 LSBs
3. Host uses IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
Unused bits in the 8-bit data memory formats are filled with 0s.
into the DSP s IDMA control registers. If Bit 15 = 1, the
The BIAD register field is used to specify the starting address
value of bits 7:0 represent the IDMA overlay: Bits 14:8 must
for the on-chip memory involved with the transfer. The 14-bit
be set to 0. If Bit 15 = 0, the value of bits 13:0 represent the
BEAD register specifies the starting address for the external byte
starting address of internal memory to be accessed and Bit 14
memory space. The 8-bit BMPAGE register specifies the start-
reflects PM or DM for access.
ing page for the external byte memory space. The BDIR register
4. Host uses IS and IRD (or IWR) to read (or write) DSP inter-
field selects the direction of the transfer. Finally, the 14-bit
nal memory (PM or DM).
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
5. Host checks IACK line to see if the DSP has completed the
previous IDMA operation.
6. Host ends IDMA transfer.
 10 REV. A
ADSP-2189M
The IDMA port has a 16-bit multiplexed address and data bus
DMA
DATA MEMORY
and supports 24-bit program memory. The IDMA port is com-
OVLAY
DMA
pletely asynchronous and can be written while the ADSP-2189M
PROGRAM MEMORY
ALWAYS
OVLAY
ACCESSIBLE
is operating at full speed.
AT ADDRESS
0 2000  0 3FFF
ALWAYS
The DSP memory address is latched and then automatically
ACCESSIBLE
0 0000
AT ADDRESS
0 1FFF
incremented after each IDMA transaction. An external device
ACCESSIBLE WHEN
0 0000  0 1FFF
0 0000
DMOVLAY = 0
can therefore access a block of sequentially addressed memory
0 2000 0 1FFF
0 3FFF
by specifying only the starting address of the block. This in-
ACCESSIBLE WHEN 0 0000
ACCESSIBLE WHEN
PMOVLAY = 0 0 2000
0 1FFF
creases throughput as the address does not have to be sent for DMOVLAY = 4
0 3FFF
0 0000
ACCESSIBLE WHEN
each memory access.
0 2000
0 1FFF
DMOVLAY = 5
ACCESSIBLE WHEN
0 3FFF
PMOVLAY = 4
0 0000
IDMA Port access occurs in two phases. The first is the IDMA ACCESSIBLE WHEN
0 1FFF
DMOVLAY = 6
ACCESSIBLE WHEN
Address Latch cycle. When the acknowledge is asserted, a 14-bit
PMOVLAY = 5
ACCESSIBLE WHEN
address and 1-bit destination type can be driven onto the bus by DMOVLAY = 7
NOTE: IDMA AND BDMA HAVEN SEPARATE
DMA CONTROL REGISTERS
an external device. The address specifies an on-chip memory
location, the destination type specifies whether it is a DM or
Figure 11. Direct Memory Access PM and DM Memory
PM access. The falling edge of the IDMA address latch signal
Maps
(IAL) or the missing edge of the IDMA select signal (IS) latches
Bootstrap Loading (Booting)
this value into the IDMAA register.
The ADSP-2189M has two mechanisms to allow automatic
Once the address is stored, data can then be either read from, or
loading of the internal program memory after reset. The method
written to, the ADSP-2189M s on-chip memory. Asserting the
for booting is controlled by the Mode A, B and C configuration
select line (IS) and the appropriate read or write line (IRD and
bits.
IWR respectively) signals the ADSP-2189M that a particular
When the MODE pins specify BDMA booting, the ADSP-2189M
transaction is required. In either case, there is a one-processor-
initiates a BDMA boot sequence when reset is released.
cycle delay for synchronization. The memory access consumes
one additional processor cycle.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
Once an access has occurred, the latched address is automati-
BIAD and BEAD registers are set to 0, the BTYPE register is
cally incremented and another access can occur.
set to 0 to specify program memory 24-bit words, and the
Through the IDMAA register, the DSP can also specify the
BWCOUNT register is set to 32. This causes 32 words of on-
starting address and data format for DMA operation. Asserting
chip program memory to be loaded from byte memory. These
the IDMA port select (IS) and address latch enable (IAL) di-
32 words are used to set up the BDMA to load in the remaining
rects the ADSP-2189M to write the address onto the IAD0-14
program code. The BCR bit is also set to 1, which causes pro-
bus into the IDMA Control Register. If Bit 15 is set to 0, IDMA
gram execution to be held off until all 32 words are loaded into
latches the address. If Bit 15 is set to 1, IDMA latches into the
on-chip program memory. Execution then begins at address 0.
OVLAY register. This register, shown below, is memory
The ADSP-2100 Family development software (Revision 5.02
mapped at address DM (0x3FE0). Note that the latched address
and later) fully supports the BDMA booting feature and can
(IDMAA) cannot be read back by the host.
generate byte memory space compatible boot code.
Refer to the following figures for more information on IDMA
The IDLE instruction can also be used to allow the processor to
and DMA memory maps.
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the ad-
IDMA OVERLAY
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
dresses to boot memory must be constructed externally to the
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DM(0 3FE7)
ADSP-2189M. The only memory address bit provided by the
processor is A0.
RESERVED SET TO 0 ID DMOVLAY ID PMOVLAY
IDMA Port Booting
IDMA CONTROL (U = UNDEFINED AT RESET) The ADSP-2189M can also boot programs through its Internal
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the
U U U U U U U U U U U U U U U DM(0 3FE0)
ADSP-2189M boots from the IDMA port. IDMA feature can
load as much on-chip memory as desired. Program execution is
IDMAA ADDRESS
IDMAD DESTINATION MEMORY TYPE:
held off until on-chip program memory location 0 is written to.
0 = PM
1 = DM
Figure 10. IDMA Control/OVLAY Registers
REV. A
 11
ADSP-2189M
Bus Request and Bus Grant
" The algebraic syntax eliminates the need to remember cryp-
The ADSP-2189M can relinquish control of the data and ad-
tic assembler mnemonics. For example, a typical arithmetic
dress buses to an external device. When the external device
add instruction, such as AR = AX0 + AY0, resembles a
requires access to memory, it asserts the bus request (BR) sig-
simple equation.
nal. If the ADSP-2189M is not performing an external memory
" Every instruction assembles into a single, 24-bit word that
access, it responds to the active BR input in the following pro-
can execute in a single instruction cycle.
cessor cycle by:
" The syntax is a superset ADSP-2100 Family assembly language
" Three-stating the data and address buses and the PMS,
and is completely source-and-object-code-compatible with
DMS, BMS, CMS, IOMS, RD, WR output drivers,
other family members. Programs may need to be relocated to
utilize on-chip memory and conform to the ADSP-2189M s
" Asserting the bus grant (BG) signal, and
interrupt vector and reset vector map.
" Halting program execution.
" Sixteen condition codes are available. For conditional jump,
If Go Mode is enabled, the ADSP-2189M will not halt program
call, return, or arithmetic instructions, the condition can be
execution until it encounters an instruction that requires an
checked and the operation executed in the same instruction
external memory access.
cycle.
If the ADSP-2189M is performing an external memory access
" Multifunction instructions allow parallel execution of an
when the external device asserts the BR signal, it will not three-
arithmetic instruction with up to two fetches or one write to
state the memory interfaces or assert the BG signal until the
processor memory space during a single instruction cycle.
processor cycle after the access completes. The instruction does
not need to be completed when the bus is granted. If a single
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
instruction requires two external memory accesses, the bus will
The ADSP-2189M has on-chip emulation support and an ICE-
be granted between the two accesses.
Port, a special set of pins that interface to the EZ-ICE. These
When the BR signal is released, the processor releases the BG
features allow in-circuit emulation without replacing the target
signal, reenables the output drivers and continues program
system processor by using only a 14-pin connection from the
execution from the point at which it stopped.
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE s in-circuit probe, a 14-pin
The bus request feature operates at all times, including when
plug.
the processor is booting and when RESET is active.
Issuing the chip reset command during emulation causes the
The BGH pin is asserted when the ADSP-2189M requires the
DSP to perform a full chip reset, including a reset of its memory
external bus for a memory or BDMA access, but is stopped.
mode. Therefore, it is vital that the mode pins are set correctly
The other device can release the bus by deasserting bus request.
PRIOR to issuing a chip reset command from the emulator user
Once the bus is released, the ADSP-2189M deasserts BG and
interface. If you are using a passive method of maintaining
BGH and executes the external memory access.
mode information (as discussed in Setting Memory Modes),
Flag I/O Pins
then it does not matter that the mode information is latched by
The ADSP-2189M has eight general purpose programmable
an emulator reset. However, if using the RESET pin as a
input/output flag pins. They are controlled by two memory
method of setting the value of the mode pins, the effects of an
mapped registers. The PFTYPE register determines the direc-
emulator reset must be taken into consideration.
tion, 1 = output and 0 = input. The PFDATA register is used to
One method of ensuring that the values located on the mode
read and write the values on the pins. Data being read from a
pins are those desired is to construct a circuit like the one shown
pin configured as an input is synchronized to the ADSP-2189M s
in Figure 12. This circuit forces the value located on the Mode
clock. Bits that are programmed as outputs will read the value
A pin to logic high; regardless if it latched via the RESET or
being output. The PF pins default to input during reset.
ERESET pin.
In addition to the programmable flags, the ADSP-2189M has
five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and
FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
ERESET
FLAG_OUT are available as an alternate configuration of
RESET
SPORT1.
ADSP-2189M
Note: Pins PF0, PF1, PF2 and PF3 are also used for device
1k
configuration during reset.
MODE A/PFO
INSTRUCTION SET DESCRIPTION
PROGRAMMABLE I/O
The ADSP-2189M assembly language instruction set has an
Figure 12. Mode A Pin/EZ-ICE Circuit
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of the
See the ADSP-2100 Family EZ-Tools data sheet for complete
processor s unique architecture, offers the following benefits:
information on ICE products.
 12 REV. A
ADSP-2189M
The ICE-Port interface consists of the following ADSP-2189M
Target Memory Interface
pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS,
For your target system to be compatible with the EZ-ICE emu-
and ELOUT.
lator, it must comply with the memory interface guidelines listed
below.
These ADSP-2189M pins must be connected only to the EZ-
ICE connector in the target system. These pins have no function
PM, DM, BM, IOM, and CM
except during emulation, and do not require pull-up or pull-
Design your Program Memory (PM), Data Memory (DM),
down resistors. The traces for these signals between the ADSP-
Byte Memory (BM), I/O Memory (IOM), and Composite
2189M and the connector must be kept as short as possible, no
Memory (CM) external interfaces to comply with worst case
longer than three inches.
device timing requirements and switching characteristics as
The following pins are also used by the EZ-ICE: BR, BG,
specified in this data sheet. The performance of the EZ-ICE
RESET, and GND.
may approach published worst case specification for some memory
access timing requirements and switching characteristics.
The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the ADSP-2189M in the target system. This causes the
Note: If your target does not meet the worst case chip specifica-
processor to use its ERESET, EBR, and EBG pins instead of
tion for memory access parameters, you may not be able to
the RESET, BR, and BG pins. The BG output is three-stated.
emulate your circuitry at the desired CLKIN frequency. De-
These signals do not need to be jumper-isolated in your system.
pending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
The EZ-ICE connects to your target system via a ribbon cable
statistically vary in switching characteristic and timing require-
and a 14-pin female plug. The female plug is plugged onto the
ments within published limits.
14-pin connector (a pin strip header) on the target board.
Restriction: All memory strobe signals on the ADSP-2189M
Target Board Connector for EZ-ICE Probe
(RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in your
The EZ-ICE connector (a standard pin strip header) is shown in
target system must have 10 k&! pull-up resistors connected when
Figure 13. You must add this connector to your target board
the EZ-ICE is being used. The pull-up resistors are necessary
design if you intend to use the EZ-ICE. Be sure to allow enough
because there are no internal pull-ups to guarantee their state
room in your system to fit the EZ-ICE probe onto the 14-pin
during prolonged three-state conditions resulting from typical
connector.
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
1 2
GND BG
Target System Interface Signals
3 4
When the EZ-ICE board is installed, the performance on some
EBG BR
system signals change. Design your system to be compatible
5 6
EBR EINT with the following system interface signal changes introduced by
7 8
the EZ-ICE board:
KEY (NO PIN) ELIN
9 10 " EZ-ICE emulation introduces an 8 ns propagation delay
ELOUT ECLK
between your target circuitry and the DSP on the RESET
11 12
signal.
EE EMS
13 14
" EZ-ICE emulation introduces an 8 ns propagation delay
RESET ERESET
between your target circuitry and the DSP on the BR signal.
TOP VIEW
" EZ-ICE emulation ignores RESET and BR when single-
Figure 13. Target Board Connector for EZ-ICE stepping.
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca- " EZ-ICE emulation ignores RESET and BR when in Emula-
tion you must remove Pin 7 from the header. The pins must tor Space (DSP halted).
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
" EZ-ICE emulation ignores the state of target BR in certain
ing should be 0.1 × 0.1 inches. The pin strip header must have
modes. As a result, the target system may take control of the
at least 0.15 inch clearance on all sides to accept the EZ-ICE
DSP s external memory bus only if bus grant (BG) is as-
probe plug.
serted by the EZ-ICE board s DSP.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
REV. A
 13
ADSP-2189M SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade B Grade
Parameter Min Max Min Max Unit
VDDINT 2.37 2.63 2.25 2.75 V
VDDEXT 2.37 3.6 2.25 3.6 V
VINPUT1 VIL =  0.3 VIH = 3.6  0.03 3.6 V
TAMB 0 +70  40 +85 °C
NOTES
1
The ADSP-2189M is 3.3 V tolerant (always accepts up to 3.6 Volt max VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT; because VOH
(max) H" VDDEXT (max). This applies to Bidirectional pins (D0 D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1 A13, PF0 PF7) and Input Only pins (CLKIN,
RESET, BR, DR0, DR1, PWD).
ELECTRICAL CHARACTERISTICS
K/B Grades
Parameter Test Conditions Min Typ Max Unit
VIH, Hi-Level Input Voltage1, 2 @VDDINT = max 1.5 V
VIH, Hi-Level CLKIN Voltage @ VDDINT = max 2.0 V
VIL, Lo-Level Input Voltage1, 3 @VDDINT = min 0.6 V
VOH, Hi-Level Output Voltage1, 4 , 5 @VDDEXT = min, IOH =  0.5 mA 2.0 V
@VDDEXT = 3.0 V, IOH =  0.5 mA 2.4 V
@VDDEXT = min, IOH =  100 µA6 VDDEXT  0.3 V
VOL, Lo-Level Output Voltage1, 4, 5 @VDDEXT = min, IOL = 2 mA 0.4 V
IIH, Hi-Level Input Current3 @VDDINT = max, VIN = 3.6 V 10 µA
IIL, Lo-Level Input Current3 @VDDINT = max, VIN = 0 V 10 µA
IOZH, Three-State Leakage Current7 @VDDINT = max, VIN = 3.6 V8 10 µA
IOZL, Three-State Leakage Current7 @VDDINT = max, VIN = 0 V8 10 µA
IDD, Supply Current (Idle)9 @VDDINT = 2.5, tCK = 15 ns 9 mA
IDD, Supply Current (Idle)9 @VDDINT = 2.5, tCK = 13.3 ns 10 mA
IDD, Supply Current (Dynamic)10 @VDDINT = 2.5, tCK = 15 ns11,
TAMB = +25°C32 mA
IDD, Supply Current (Dynamic)10 @VDDINT = 2.5, tCK = 13.3 ns11,
TAMB = +25°C36 mA
IDD, Supply Current (Power-Down)12, 15 Lowest Power Mode 150 µA
CI, Input Pin Capacitance3, 6, 13 @VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = +25°C8 pF
CO, Output Pin Capacitance6, 7, 12, 14 @VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = +25°C8 pF
NOTES
1
Bidirectional pins: D0 D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1 A13, PF0 PF7.
2
Input Only pins: RESET, BR, DR0, DR1, PWD.
3
Input Only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4
Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH.
5
Although specified for TTL outputs, all ADSP-2189M outputs are CMOS-compatible and will drive to V and GND, assuming no dc loads.
DDEXT
6
Guaranteed but not tested.
7
Three-statable pins: A0 A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0 PF7.
8
0 V on BR.
9
Idle refers to ADSP-2189M state of operation during execution of IDLE instruction. Deasserted pins are driven to either V or GND.
DD
10
IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.
11
VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
12
See Chapter 9 of the ADSP-2100 Family User s Manual, Third Edition for details.
13
Applies to LQFP package type.
14
Output pin capacitance is the capacitive load for any three-stated output pin.
15
VDDINT = 2.5 V. T = 25°C.
Specifications subject to change without notice.
 14 REV. A
ADSP-2189M
ABSOLUTE MAXIMUM RATINGS1
Value
Parameter Min Max
Internal Supply Voltage (VDDINT)  0.3 V +3.0 V
External Supply Voltage (VDDEXT)  0.3 V +4.6 V
Input Voltage2  0.5 V +4.6 V
Output Voltage Swing3  0.5 V VDDEXT + 0.5 V
Operating Temperature Range (Ambient)  40°C +85°C
Storage Temperature Range  65°C +150°C
Lead Temperature (5 sec) LQFP +280°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Applies to Bidirectional pins (D0 D23, RFS0, RFS1, SCLK0, SCLK1, TFS0,
TFS1, A1 A13, PF0 PF7) and Input only pins (CLKIN, RESET, BR, DR0,
DR1, PWD).
3
Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK,
A0, DT0, DT1, CLKOUT, FL2-0, BGH).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
WARNING!
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-2189M features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.
MEMORY TIMING SPECIFICATIONS
TIMING PARAMETERS
The table below shows common memory device specifications
GENERAL NOTES
and the corresponding ADSP-2189M timing parameters, for
Use the exact timing information given. Do not attempt to
your convenience.
derive parameters from the addition or subtraction of others.
Memory Timing
While addition or subtraction would yield meaningful results for
Device Parameter
an individual device, the values given in this data sheet reflect
Specification Parameter Definition1
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
Address Setup to tASW A0 A13, xMS Setup before
Write Start WR Low
TIMING NOTES
Address Setup to tAW A0 A13, xMS Setup before
Switching characteristics specify how the processor changes its
Write End WR Deasserted
signals. You have no control over this timing circuitry external
Address Hold Time tWRA A0 A13, xMS Hold before
to the processor must be designed for compatibility with these
WR Low
signal characteristics. Switching characteristics tell you what the
Data Setup Time tDW Data Setup before WR
processor will do in a given circumstance. You can also use
High
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is Data Hold Time tDH Data Hold after WR High
satisfied.
OE to Data Valid tRDD RD Low to Data Valid
Timing requirements apply to signals that are controlled by Address Access Time tAA A0 A13, xMS to Data Valid
circuitry external to the processor, such as the data input for a
NOTE
read operation. Timing requirements guarantee that the proces- 1
xMS = PMS, DMS, BMS, CMS or IOMS.
sor operates correctly with other devices.
REV. A
 15
ADSP-2189M
FREQUENCY DEPENDENCY FOR TIMING Output Drive Currents
SPECIFICATIONS Figure 14 shows typical I-V characteristics for the output drivers
tCK is defined as 0.5tCKI. The ADSP-2189M uses an input clock on the ADSP-2189M. The curves represent the current drive
with a frequency equal to half the instruction rate: a 37.50 MHz capability of the output drivers as a function of output voltage.
input clock (which is equivalent to 28 ns) yields a 13 ns proces-
80
sor cycle (equivalent to 75 MHz). tCK values within the range of
0.5tCKI period should be substituted for all relevant timing pa-
VOH
60
VDDEXT = 3.6V @  40 C
rameters to obtain the specification value.
40
Example: tCKH = 0.5tCK  7 ns = 0.5 (15 ns)  7 ns = 0.5 ns
VDDEXT = 3.3V @ +25 C
20
ENVIRONMENTAL CONDITIONS1
VDDEXT = 2.5V @ +85 C
0
Rating Description Symbol Value
 20
VDDEXT = 3.6V @  40 C
Thermal Resistance
(Case-to-Ambient) ¸CA 48°C/W
VOL VDDEXT = 2.5V @ +85 C
 40
(Junction-to-Ambient) ¸JA 50°C/W
VDDEXT = 3.3V @ +25 C
(Junction-to-Case) ¸JC 2°C/W  60
NOTE
 80
1 0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Where the ambient temperature rating (TAMB) is:
SOURCE VOLTAGE  V
TAMB = TCASE  (PD × ¸CA)
TCASE = Case temperature in °C
Figure 14. Typical Output Driver Characteristics
PD = Power dissipation in W.
POWER DISSIPATION
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 × f
C = load capacitance, f = output switching frequency.
Example:
In an application where external data memory is used and no
other outputs are active, power dissipation is calculated as follows:
Assumptions:
" External data memory is accessed every cycle with 50% of
the address pins switching.
" External data memory writes occur every other cycle with
50% of the data pins switching.
" Each address and data pin has a 10 pF total load at the pin.
" The application operates at VDDEXT = 3.3 V and tCK = 15 ns.
Total Power Dissipation = PINT + (C × VDDEXT2 × f)
PINT = internal power dissipation from Power vs. Frequency
graph (Figure 15).
(C × VDDEXT2 × f) is calculated for each output:
# of
Parameters Pins C VDDEXT2 fPD
Address, DMS 8 10 pF 3.32 V 33.3 MHz 29.0 mW
Data Output, WR 9 10 pF 3.32 V 16.67 MHz 16.3 mW
RD 1 10 pF 3.32 V 16.67 MHz 1.8 mW
CLKOUT 1 10 pF 3.32 V 33.3 MHz 3.6 mW
50.7 mW
Total power dissipation for this example is PINT + 50.7 mW.
 16 REV. A
SOURCE CURRENT  mA
ADSP-2189M
CAPACITIVE LOADING
2189L POWER, INTERNAL1, 2, 3
115
Figure 16 and Figure 17 show the capacitive loading character-
110mW
110
istics of the ADSP-2189M.
105
100 VDD = 2.65V
30
95mW
T = +85 C
95
VDD = 0V TO 2.0V
90
25
VDD = 2.5V
85
82mW 82mW
80
VDD = 2.35V 20
75
70mW
70
65 15
61mW
60
55
10
50 55 60 65 70 75 80
1/tCK  MHz
5
POWER, IDLE1, 2, 4
30
28mW
0
28
VDD = 2.65V 0 50 100 150 200 250 300
CL  pF
26
24mW 24mW
Figure 16. Typical Output Rise Time vs. Load Capacitance,
24
VDD = 2.5V
CL (at Maximum Ambient Operating Temperature)
22
20mW 20mW
18
20
VDD = 2.35V
16
18
16.5mW 14
16
12
14 10
40 55 60 65 70 75 80
1/tCK  MHz 8
6
POWER, IDLE n MODES2
26
4
24mW
IDLE
2
24
VDD = 2.65V
NOMINAL
22
 2
20mW
 4
20
 6
0 50 100 150 200 250
18
CL  pF
16.4mW
VDD = 2.5V
IDLE (16)
16 Figure 17. Typical Output Valid Delay or Hold vs. Load
15mW
IDLE (128)
Capacitance, CL (at Maximum Ambient Operating
VDD = 2.35V
14
15.7mW
14.25mW Temperature)
12
50 55 60 65 70 75 80
900
1/tCK  MHz
VALID FOR ALL TEMPERATURE GRADES. 772 A
800
TEMP = +85 C
1
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
657 A
2
TYPICAL POWER DISSIPATION AT 2.5V VDDINT AND +25 C EXCEPT 700
WHERE SPECIFIED.
3
IDD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM 600
INTERNAL MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION
475 A
(TYPES 1, 4, 5, 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE
500
TEMP = +70 C
IDLE INSTRUCTIONS.
393 A
4
IDLE REFERS TO ADSP-2189M STATE OF OPERATION DURING EXECUTION
400
OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD
OR GND.
300
TEMP = +25 C 161 A
Figure 15. Power vs. Frequency 200
131 A
100
0
2.25 2.35 2.5 2.65 2.75
VDD INTERNAL  Volts
Figure 18. IDD Power-Down
REV. A
 17
INT
POWER (P
)  mW
RISE TIME (0.4V 2.4V)  ns
IDLE
POWER (P
)  mW
VALID OUTPUT DELAY OR HOLD  ns
IDLE
POWER (P
n
)  mW
CURRENT 

A
ADSP-2189M
driving. The output enable time (tENA) is the interval from when
TEST CONDITIONS
a reference signal reaches a high or low voltage level to when the
Output Disable Time
output has reached a specified high or low trip point, as shown
Output pins are considered to be disabled when they have
in the Output Enable/Disable diagram. If multiple pins (such as
stopped driving and started a transition from the measured
the data bus) are enabled, the measurement value is that of the
output high or low voltage to a high impedance state. The out-
first pin to start driving.
put disable time (tDIS) is the difference of tMEASURED and tDECAY,
as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low REFERENCE
SIGNAL
voltage level to when the output voltages have changed by 0.5 V
tMEASURED
from the measured output high or low voltage.
tENA
tDIS
VOH VOH
The decay time, tDECAY, is dependent on the capacitive load,
(MEASURED) (MEASURED)
CL, and the current load, iL, on the output pin. It can be ap-
VOH (MEASURED)  0.5V
2.0V
proximated by the following equation: OUTPUT
1.0V
VOL (MEASURED) +0.5V
VOL VOL
CL × 0.5 V
tDECAY
tDECAY = (MEASURED) (MEASURED)
iL
OUTPUT
OUTPUT STOPS STARTS
DRIVING DRIVING
from which
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
tDIS = tMEASURED  tDECAY
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
is calculated. If multiple pins (such as the data bus) are disabled,
Figure 20. Output Enable/Disable
the measurement value is that of the last pin to stop driving.
IOL
INPUT
1.5V
2.0V TO
OUTPUT 1.5V OUTPUT +1.5V
0.8V PIN
50pF
Figure 19. Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable)
IOH
Output Enable Time
Output pins are considered to be enabled when they have made
Figure 21. Equivalent Device Loading for AC Measure-
a transition from a high impedance state to when they start
ments (Including All Fixtures)
 18 REV. A
ADSP-2189M
TIMING PARAMETERS
Parameter Min Max Unit
Clock Signals and Reset
Timing Requirements:
tCKI CLKIN Period 26.6 80 ns
tCKIL CLKIN Width Low 13 ns
tCKIH CLKIN Width High 13 ns
Switching Characteristics:
tCKL CLKOUT Width Low 0.5tCK  2ns
tCKH CLKOUT Width High 0.5tCK  2ns
tCKOH CLKIN High to CLKOUT High 0 13 ns
Control Signals
Timing Requirements:
tRSP RESET Width Low 5tCK1 ns
tMS Mode Setup before RESET High 2 ns
tMH Mode Hold after RESET High 5 ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
PF(3:0)*
tMS tMH
RESET
*PF3 IS MODE D, PF2 IS MODE C, PF0 IS MODE A
Figure 22. Clock Signals
REV. A
 19
ADSP-2189M
Parameter Min Max Unit
Interrupts and Flags
Timing Requirements:
tIFS IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4 0.25tCK + 10 ns
tIFH IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4 0.25tCK ns
Switching Characteristics:
tFOH Flag Output Hold after CLKOUT Low5 0.5tCK  5ns
tFOD Flag Output Delay from CLKOUT Low5 0.5tCK + 4 ns
NOTES
1
If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User s Manual, Third Edition, for further
information on interrupt servicing.)
2
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag Outputs = PFx, FL0, FL1, FL2, Flag_out4.
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
PFx
tIFS
Figure 23. Interrupts and Flags
 20 REV. A
ADSP-2189M
Parameter Min Max Unit
Bus Request Bus Grant
Timing Requirements:
tBH BR Hold after CLKOUT High1 0.25tCK + 2 ns
tBS BR Setup before CLKOUT Low1 0.25tCK + 10 ns
Switching Characteristics:
tSD CLKOUT High to xMS, RD, WR Disable 0.25tCK + 8 ns
tSDB xMS, RD, WR Disable to BG Low 0 ns
tSE BG High to xMS, RD, WR Enable 0 ns
tSEC xMS, RD, WR Enable to CLKOUT High 0.25tCK  3ns
tSDBH xMS, RD, WR Disable to BGH Low2 0ns
tSEH BGH High to xMS, RD, WR Enable2 0ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User s Manual, Third Edition, for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR tSD
tSEC
BG
tSDB
tSE
BGH
tSDBH
tSEH
Figure 24. Bus Request Bus Grant
REV. A
 21
ADSP-2189M
Parameter Min Max Unit
Memory Read
Timing Requirements:
tRDD RD Low to Data Valid 0.5tCK  5 + w ns
tAA A0 A13, xMS to Data Valid 0.75tCK  6 + w ns
tRDH Data Hold from RD High 0 ns
Switching Characteristics:
tRP RD Pulsewidth 0.5tCK  3 + w ns
tCRD CLKOUT High to RD Low 0.25tCK  2 0.25tCK + 4 ns
tASR A0 A13, xMS Setup before RD Low 0.25tCK  3ns
tRDA A0 A13, xMS Hold after RD Deasserted 0.25tCK  3ns
tRWR RD High to RD or WR Low 0.5tCK  3ns
w = wait-states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0  A13
DMS, PMS,
BMS, IOMS,
CMS
tRDA
RD
tASR
tRP
tRWR
tCRD
D
tRDD
tRDH
tAA
WR
Figure 25. Memory Read
 22 REV. A
ADSP-2189M
Parameter Min Max Unit
Memory Write
Switching Characteristics:
tDW Data Setup before WR High 0.5tCK  4 + w ns
tDH Data Hold after WR High 0.25tCK  1ns
tWP WR Pulsewidth 0.5tCK  3 + w ns
tWDE WR Low to Data Enabled 0 ns
tASW A0 A13, xMS Setup before WR Low 0.25tCK  3ns
tDDR Data Disable before WR or RD Low 0.25tCK  3ns
tCWR CLKOUT High to WR Low 0.25tCK  2 0.25tCK + 4 ns
tAW A0 A13, xMS, Setup before WR Deasserted 0.75tCK  5 + w ns
tWRA A0 A13, xMS Hold after WR Deasserted 0.25tCK  1ns
tWWR WR High to RD or WR Low 0.5tCK  3ns
w = wait-states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0 A13
DMS, PMS,
BMS, CMS,
IOMS
tWRA
WR
tWWR
tASW tWP
tAW
tDH tDDR
tCWR
D
tDW
tWDE
RD
Figure 26. Memory Write
REV. A
 23
ADSP-2189M
Parameter Min Max Unit
Serial Ports
Timing Requirements:
tSCK SCLK Period 26.67 ns
tSCS DR/TFS/RFS Setup before SCLK Low 4 ns
tSCH DR/TFS/RFS Hold after SCLK Low 7 ns
tSCP SCLKIN Width 12 ns
Switching Characteristics:
tCC CLKOUT High to SCLKOUT 0.25tCK 0.25tCK + 6 ns
tSCDE SCLK High to DT Enable 0 ns
tSCDV SCLK High to DT Valid 12 ns
tRH TFS/RFSOUT Hold after SCLK High 0 ns
tRD TFS/RFSOUT Delay from SCLK High 12 ns
tSCDH DT Hold after SCLK High 0 ns
tTDE TFS (Alt) to DT Enable 0 ns
tTDV TFS (Alt) to DT Valid 12 ns
tSCDD SCLK High to DT Disable 12 ns
tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid 12 ns
CLKOUT
tCC tCC
tSCK
SCLK
tSCP
tSCP
tSCS tSCH
DR
TFSIN
RFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFSOUT
ALTERNATE
FRAME MODE
tRDV
RFSOUT
MULTICHANNEL
MODE,
FRAME DELAY 0
tTDE
(MFD = 0)
tTDV
TFSIN
ALTERNATE
FRAME MODE
tRDV
RFSIN
MULTICHANNEL
MODE,
FRAME DELAY 0
(MFD = 0)
Figure 27. Serial Ports
 24 REV. A
ADSP-2189M
Parameter Min Max Unit
IDMA Address Latch
Timing Requirements:
tIALP Duration of Address Latch1, 2 10 ns
tIASU IAD15 0 Address Setup before Address Latch End2 5ns
tIAH IAD15 0 Address Hold after Address Latch End2 3ns
tIKA IACK Low before Start of Address Latch2, 3 0ns
tIALS Start of Write or Read after Address Latch End2, 3 3ns
tIALD Address Latch Start after Address Latch End1, 2 2ns
NOTES
1
Start of Address Latch = IS Low and IAL High.
2
End of Address Latch = IS High or IAL Low.
3
Start of Write or Read = IS Low and IWR Low or IRD Low.
IACK
tIKA
tIALD
IAL
tIALP tIALP
IS
IAD15 0
tIASU tIASU
tIAH tIAH
tIALS
RD OR WR
Figure 28. IDMA Address Latch
REV. A
 25
ADSP-2189M
Parameter Min Max Unit
IDMA Write, Short Write Cycle
Timing Requirements:
tIKW IACK Low before Start of Write1 0ns
tIWP Duration of Write1, 2 10 ns
tIDSU IAD15 0 Data Setup before End of Write2, 3, 4 3ns
tIDH IAD15 0 Data Hold after End of Write2, 3, 4 2ns
Switching Characteristics:
tIKHW Start of Write to IACK High 10 ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
End of Write = IS High or IWR High.
3
If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH.
4
If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.
tIKW
IACK
tIKHW
IS
tIWP
IWR
tIDH
tIDSU
IAD 15 0 DATA
Figure 29. IDMA Write, Short Write Cycle
 26 REV. A
ADSP-2189M
Parameter Min Max Unit
IDMA Write, Long Write Cycle
Timing Requirements:
tIKW IACK Low before Start of Write1 0ns
tIKSU IAD15 0 Data Setup before End of Write2, 3, 4 0.5tCK + 5 ns
tIKH IAD15 0 Data Hold after End of Write2, 3, 4 0ns
Switching Characteristics:
tIKLW Start of Write to IACK Low4 1.5tCK ns
tIKHW Start of Write to IACK High 10 ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH.
3
If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.
4
This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User s Manual, Third Edition.
tIKW
IACK
tIKHW
tIKLW
IS
IWR
tIKSU
tIKH
IAD15 0 DATA
Figure 30. IDMA Write, Long Write Cycle
REV. A
 27
ADSP-2189M
Parameter Min Max Unit
IDMA Read, Long Read Cycle
Timing Requirements:
tIKR IACK Low before Start of Read1 0ns
tIRK End of Read after IACK Low2 2ns
Switching Characteristics:
tIKHR IACK High after Start of Read1 10 ns
tIKDS IAD15 0 Data Setup before IACK Low 0.5tCK  2ns
tIKDH IAD15 0 Data Hold after End of Read2 0ns
tIKDD IAD15 0 Data Disabled after End of Read2 10 ns
tIRDE IAD15 0 Previous Data Enabled after Start of Read 0 ns
tIRDV IAD15 0 Previous Data Valid after Start of Read 11 ns
tIRDH1 IAD15 0 Previous Data Hold after Start of Read (DM/PM1)3 2tCK  3ns
tIRDH2 IAD15 0 Previous Data Hold after Start of Read (PM2)4 tCK  5ns
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
3
DM read or first half of PM read.
4
Second half of PM read.
IACK
tIKHR
tIKR
IS
tIRK
IRD
tIKDH
tIKDS
tIRDE
PREVIOUS READ
IAD15 0
DATA DATA
tIRDV tIKDD
tIRDH
Figure 31. IDMA Read, Long Read Cycle
 28 REV. A
ADSP-2189M
Parameter Min Max Unit
IDMA Read, Short Read Cycle
Timing Requirements:
tIKR IACK Low before Start of Read1 0ns
tIRP Duration of Read 10 ns
Switching Characteristics:
tIKHR IACK High after Start of Read1 10 ns
tIKDH IAD15 0 Data Hold after End of Read2 0ns
tIKDD IAD15 0 Data Disabled after End of Read2 10 ns
tIRDE IAD15 0 Previous Data Enabled after Start of Read 0 ns
tIRDV IAD15 0 Previous Data Valid after Start of Read 10 ns
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
IACK
tIKR
tIKHR
IS
tIRP
IRD
tIKDH
tIRDE
PREVIOUS
IAD15 0
DATA
tIKDD
tIRDV
Figure 32. IDMA Read, Short Read Cycle
REV. A
 29
ADSP-2189M
100-Lead LQFP Package Pinout
A4/IAD3 1 75
D15
PIN 1
A5/IAD4 2 74 D14
IDENTIFIER
GND 3 73 D13
A6/IAD5 4 72
D12
A7/IAD6 5 71 GND
A8/IAD7 6 70
D11
A9/IAD8 7 69 D10
A10/IAD9 8 68
D9
9 67 VDDEXT
A11/IAD10
A12/IAD11 10 66 GND
A13/IAD12 11 65
D8
GND 12 64 D7/IWR
ADSP-2189M
CLKIN 13 63 D6/IRD
TOP VIEW
XTAL 14 62 D5/IAL
(Not to Scale)
VDDEXT 15 61
D4/IS
16 60
CLKOUT GND
GND 17 59 VDDINT
D3/IACK
VDDINT 18 58
19 57 D2/IAD15
WR
RD 20 56 D1/IAD14
21 55
BMS D0/IAD13
DMS 22 54
BG
PMS 23 53
EBG
24 52
IOMS
BR
25 51
CMS EBR
 30 REV. A
DDEXT
A0
PWD
A2/IAD1
FL2
D16
PF0 [MODE A]
FL0
D17
D21
D20
D18
PWDACK
D22
D19
D23
PF2 [MODE C]
91
88
PF3
86
FL1
83
81
78
95
BGH
94
92
GND
90 V
89
87
85
84
82
80 GND
79
77
76
98
A1/IAD0
96
93
PF1 [MODE B]
99
97
100 A3/IAD2
40
50
45
48
28
36
33
41
42
35
47
31
26
34
EE
46
DT1
37
DT0
DR1
DR0
EMS
EINT
GND
GND
ELIN
49
TFS1
38
TFS0
32
RFS0
RFS1
39
ECLK
DDEXT
SCLK0
SCLK1
RESET
44
ELOUT
V
ERESET
43
IRQ2
+PF7
30
IRQE
+PF4
IRQL0
+PF5
27
IRQL1
+PF6
29
ADSP-2189M
The ADSP-2189M package pinout appears in the following table. Pin names in bold text replace the plain text named functions
when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed
in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.
PIN CONFIGURATION
LQFP LQFP LQFP LQFP
Number Pin Name Number Pin Name Number Pin Name Number Pin Name
1 A4/IAD3 26 IRQE + PF4 51 EBR 76 D16
2 A5/IAD4 27 IRQL0 + PF5 52 BR 77 D17
3 GND 28 GND 53 EBG 78 D18
4 A6/IAD5 29 IRQL1 + PF6 54 BG 79 D19
5 A7/IAD6 30 IRQ2 + PF7 55 D0/IAD13 80 GND
6 A8/IAD7 31 DT0 56 D1/IAD14 81 D20
7 A9/IAD8 32 TFS0 57 D2/IAD15 82 D21
8 A10/IAD9 33 RFS0 58 D3/IACK 83 D22
9 A11/IAD10 34 DR0 59 VDDINT 84 D23
10 A12/IAD11 35 SCLK0 60 GND 85 FL2
11 A13/IAD12 36 VDDEXT 61 D4/IS 86 FL1
12 GND 37 DT1 62 D5/IAL 87 FL0
13 CLKIN 38 TFS1 63 D6/IRD 88 PF3 [Mode D]
14 XTAL 39 RFS1 64 D7/IWR 89 PF2 [Mode C]
15 VDDEXT 40DR1 65D8 90VDDEXT
16 CLKOUT 41 GND 66 GND 91 PWD
17 GND 42 SCLK1 67 VDDEXT 92 GND
18 VDDINT 43 ERESET 68 D9 93 PF1 [Mode B]
19 WR 44 RESET 69 D10 94 PF0 [Mode A]
20 RD 45 EMS 70 D11 95 BGH
21 BMS 46 EE 71 GND 96 PWDACK
22 DMS 47 ECLK 72 D12 97 A0
23 PMS 48 ELOUT 73 D13 98 A1/IAD0
24 IOMS 49 ELIN 74 D14 99 A2/IAD1
25 CMS 50 EINT 75 D15 100 A3/IAD2
REV. A
 31
ADSP-2189M
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
100-Lead Metric Thin Plastic Quad Flatpack
(ST-100)
0.638 (16.20)
0.630 (16.00) TYP SQ
0.622 (15.80)
0.553 (14.05)
0.551 (14.00) TYP SQ
0.549 (13.95)
0.063 (1.60) MAX
0.472 (12.00) BSC
0.030 (0.75)
0.024 (0.60) TYP
100 76
0.020 (0.50) 12
1 75
TYP
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.003
(0.08)
25 51
MAX LEAD
26 50
COPLANARITY 6 Ä… 4
0  7
0.007 (0.177) 0.020 (0.50)
0.011 (0.27)
BSC
0.005 (0.127) TYP
0.009 (0.22) TYP
0.003 (0.077)
LEAD PITCH
0.007 (0.17)
LEAD WIDTH
NOTE:
THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08) 0.0032 FROM
ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION.
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED
ORDERING GUIDE
Part Number Ambient Temperature Range Instruction Rate Package Description* Package Option
ADSP-2189MKST-300 0°C to +70°C 75 MHz 100-Lead LQFP ST-100
ADSP-2189MBST-266  40°C to +85°C 66 MHz 100-Lead LQFP ST-100
*In 1998, JEDEC reevaluated the specifications for the TQFP package designation, assigning it to packages 1.0 mm thick. Previously labelled TQFP packages
(1.6 mm thick) are now designated as LQFP.
 32
REV. A
C3605a 0 4/00 (rev. A)
PRINTED IN U.S.A.