a
DSP Microcomputer
ADSP-2184
FUNCTIONAL BLOCK DIAGRAM
FEATURES
PERFORMANCE
POWER-DOWN
CONTROL
FULL MEMORY
25 ns Instruction Cycle Time 40 MIPS Sustained
MODE
MEMORY PROGRAMMABLE
Performance
DATA ADDRESS
I/O
GENERATORS PROGRAM 4K 24 4K 16 EXTERNAL
AND
Single-Cycle Instruction Execution SEQUENCER PROGRAM DATA ADDRESS
FLAGS
DAG 1 DAG 2 BUS
MEMORY MEMORY
Single-Cycle Context Switch
EXTERNAL
DATA
3-Bus Architecture Allows Dual Operand Fetches in
PROGRAM MEMORY ADDRESS
BUS
Every Instruction Cycle
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
Multifunction Instructions
PROGRAM MEMORY DATA
Power-Down Mode Featuring Low CMOS Standby
OR
DATA MEMORY DATA
Power Dissipation with 200 Cycle Recovery from EXTERNAL
DATA
Power-Down Condition BUS
ARITHMETIC UNITS SERIAL PORTS TIMER
Low Power Dissipation in Idle Mode INTERNAL
ALU MAC SHIFTER SPORT 0 SPORT 1 DMA
PORT
INTEGRATION
ADSP-2100 BASE
HOST MODE
ARCHITECTURE
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
20K Bytes of On-Chip RAM, Configured as
Six External Interrupts
4K Words On-Chip Program Memory RAM and
13 Programmable Flag Pins Provide Flexible System
4K Words On-Chip Data Memory RAM
Signaling
Dual Purpose Program Memory for Both Instruction
UART Emulation through Software SPORT Reconfiguration
and Data Storage
ICE-Port"! Emulator Interface Supports Debugging
Independent ALU, Multiplier/Accumulator and Barrel
in Final Systems
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
GENERAL DESCRIPTION
Zero Overhead Looping Conditional Instruction
The ADSP-2184 is a single-chip microcomputer optimized for
Execution
digital signal processing (DSP) and other high speed numeric
Programmable 16-Bit Interval Timer with Prescaler
processing applications.
100-Lead LQFP
The ADSP-2184 combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
SYSTEM INTERFACE
a program sequencer) with two serial ports, a 16-bit internal
16-Bit Internal DMA Port for High Speed Access to
DMA port, a byte DMA port, a programmable timer, Flag I/O,
On-Chip Memory (Mode Selectable)
extensive interrupt capabilities and on-chip program and data
4 MByte Byte Memory Interface for Storage of Data
memory.
Tables and Program Overlays (Made Selectable)
8-Bit DMA to Byte Memory for Transparent Program
The ADSP-2184 integrates 20K bytes of on-chip memory con-
and Data Memory Transfers (Mode Selectable)
figured as 4K words (24-bit) of program RAM and 4K words
I/O Memory Interface with 2048 Locations Supports
(16-bit) of data RAM. Power-down circuitry is also provided to
Parallel Peripherals (Mode Selectable)
meet the low power needs of battery operated portable equip-
Programmable Memory Strobe and Separate I/O Memory
ment. The ADSP-2184 is available in 100-lead LQFP package.
Space Permits  Glueless System Design
In addition, the ADSP-2184 supports instructions that include
(Mode Selectable)
bit manipulations bit set, bit clear, bit toggle, bit test ALU
Programmable Wait State Generation
constants, multiplication instruction (x squared), biased round-
Two Double-Buffered Serial Ports with Companding
ing, result free ALU operations, I/O memory transfers, and
Hardware and Automatic Data Buffering
global interrupt masking for increased flexibility.
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or Fabricated in a high speed, double metal, low power, CMOS
Through Internal DMA Port process, the ADSP-2184 operates with a 25 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
ICE-Port is a trademark of Analog Devices, Inc.
All trademarks are the property of their respective holders.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
use, nor for any infringements of patents or other rights of third parties
Tel: [phone] World Wide Web Site: http://www.analog.com
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices. Fax: [phone] © Analog Devices, Inc., 1999
ADSP-2184
The EZ-ICE performs a full range of functions, including:
The ADSP-21xx family DSPs contain a shadow bank register
that is useful for single cycle context switching of the processor.
" In-target operation
" Up to 20 breakpoints
The ADSP-2184 s flexible architecture and comprehensive
" Single-step or full-speed operation
instruction set allow the processor to perform multiple opera-
" Registers and memory values can be examined and altered
tions in parallel. In one processor cycle the ADSP-2184 can:
" PC upload and download functions
" Generate the next program address
" Instruction-level emulation of program booting and execution
" Fetch the next instruction
" Complete assembly and disassembly of instructions
" Perform one or two data moves
" C source-level debugging
" Update one or two data address pointers
See Designing An EZ-ICE-Compatible Target System in the
" Perform a computational operation
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections), as
This takes place while the processor continues to:
well as the Target Board Connector for EZ-ICE Probe section
" Receive and transmit data through the two serial ports
of this data sheet, for the exact specifications of the EZ-ICE
" Receive or transmit data through the internal DMA port
target board connector.
" Receive or transmit data through the byte DMA port
" Decrement timer Additional Information
This data sheet provides a general overview of ADSP-2184
Development System
functionality. For additional information on the architecture and
The ADSP-2100 Family Development Software, a complete set
instruction set of the processor, refer to the ADSP-2100 Family
of tools for software and hardware system development, sup-
User s Manual, Third Edition. For more information about the
ports the ADSP-2184. The System Builder provides a high level
development tools, refer to the ADSP-2100 Family Development
method for defining the architecture of systems under develop-
Tools Data Sheet.
ment. The Assembler has an algebraic syntax that is easy to
program and debug. The Linker combines object files into an
ARCHITECTURE OVERVIEW
executable file. The Simulator provides an interactive instruction-
The ADSP-2184 instruction set provides flexible data moves
level simulation with a reconfigurable user interface to display
and multifunction (one or two data moves with a computation)
different portions of the hardware environment. A PROM
instructions. Every instruction can be executed in a single pro-
Splitter generates PROM programmer compatible files. The
cessor cycle. The ADSP-2184 assembly language uses an alge-
C Compiler, based on the Free Software Foundation s GNU
braic syntax for ease of coding and readability. A comprehensive
C Compiler, generates ADSP-2184 assembly source code.
set of development tools supports program development.
The source code debugger allows programs to be corrected in
the C environment. The Runtime Library includes over 100
POWER-DOWN
ANSI-standard mathematical and DSP-specific functions.
CONTROL
FULL MEMORY
MODE
MEMORY PROGRAMMABLE
The EZ-KIT Lite is a hardware/software kit offering a complete
DATA ADDRESS
I/O
GENERATORS PROGRAM 4K 24 4K 16 EXTERNAL
AND
development environment for the entire ADSP-21xx family: an SEQUENCER PROGRAM DATA ADDRESS
FLAGS
DAG 1 DAG 2 BUS
MEMORY MEMORY
ADSP-218x based evaluation board with PC monitor software
EXTERNAL
plus Assembler, Linker, Simulator and PROM Splitter software. DATA
PROGRAM MEMORY ADDRESS
BUS
The ADSP-21xx EZ-KIT Lite is a low cost, easy to use hardware
DATA MEMORY ADDRESS
BYTE DMA
platform on which you can quickly get started with your DSP soft- CONTROLLER
PROGRAM MEMORY DATA
ware design. The EZ-KIT Lite includes the following features:
OR
DATA MEMORY DATA
EXTERNAL
" 33 MHz ADSP-2181
DATA
BUS
" Full 16-bit Stereo Audio I/O with AD1847 SoundPort®
ARITHMETIC UNITS SERIAL PORTS TIMER
INTERNAL
Codec
ALU MAC SHIFTER SPORT 0 SPORT 1 DMA
PORT
" RS-232 Interface to PC with Microsoft Windows® 3.1
ADSP-2100 BASE
HOST MODE
Control Software ARCHITECTURE
" EZ-ICE® Connector for Emulator Control
Figure 1. Block Diagram
" DSP Demo Programs
Figure 1 is an overall block diagram of the ADSP-2184. The
The ADSP-218x EZ-ICE Emulator aids in the hardware debug-
processor contains three independent computational units: the
ging of an ADSP-2184 system. The emulator consists of hard-
ALU, the multiplier/accumulator (MAC) and the shifter. The
ware, host computer resident software, and the target board
computational units process 16-bit data directly and have provi-
connector. The ADSP-2184 integrates on-chip emulation sup-
sions to support multiprecision computations. The ALU per-
port with a 14-pin ICE-Port interface. This interface provides a
forms a standard set of arithmetic and logic operations; division
simpler target board connection that requires fewer mechanical
primitives are also supported. The MAC performs single-cycle
clearance considerations than other ADSP-2100 Family EZ-
multiply, multiply/add and multiply/subtract operations with
ICEs. The ADSP-2184 device need not be removed from the
40 bits of accumulation. The shifter performs logical and arith-
target system when using the EZ-ICE, nor are any adapters
metic shifts, normalization, denormalization and derive expo-
needed. Due to the small footprint of the EZ-ICE connector,
nent operations.
emulation can be supported in final board designs.
The shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.
SoundPort and EZ-ICE are registered trademarks of Analog Devices, Inc.
Windows is a registered trademark of Microsoft Corporation.
REV. 0
 2
ADSP-2184
wide variety of framed or frameless data transmit and receive
The internal result (R) bus connects the computational units so
modes of operation.
the output of any unit may be the input of any unit on the next
cycle.
Each port can generate an internal programmable serial clock or
A powerful program sequencer and two dedicated data address accept an external serial clock.
generators ensure efficient delivery of operands to these compu-
The ADSP-2184 provides up to 13 general-purpose flag pins.
tational units. The sequencer supports conditional jumps, sub-
The data input and output pins on SPORT1 can be alternatively
routine calls and returns in a single cycle. With internal loop
configured as an input flag and an output flag. In addition, eight
counters and loop stacks, the ADSP-2184 executes looped code
flags are programmable as inputs or outputs, and three flags are
with zero overhead; no explicit jump instructions are required to
always outputs.
maintain loops.
A programmable interval timer generates periodic interrupts. A
Two data address generators (DAGs) provide addresses for
16-bit count register (TCOUNT) decrements every n processor
simultaneous dual operand fetches from data memory and pro-
cycle, where n is a scaling value stored in an 8-bit register
gram memory. Each DAG maintains and updates four address
(TSCALE). When the value of the count register reaches zero,
pointers. Whenever the pointer is used to access data (indirect
an interrupt is generated and the count register is reloaded from
addressing), it is post-modified by the value of one of four pos-
a 16-bit period register (TPERIOD).
sible modify registers. A length value may be associated with
Serial Ports
each pointer to implement automatic modulo addressing for
The ADSP-2184 incorporates two complete synchronous serial
circular buffers.
ports (SPORT0 and SPORT1) for serial communications and
Efficient data transfer is achieved with the use of five internal
multiprocessor communication.
buses:
Here is a brief list of the capabilities of the ADSP-2184 SPORTs.
" Program Memory Address (PMA) Bus
For additional information on Serial Ports, refer to the ADSP-
" Program Memory Data (PMD) Bus
2100 Family User s Manual, Third Edition.
" Data Memory Address (DMA) Bus
" SPORTs are bidirectional and have a separate, double-buff-
" Data Memory Data (DMD) Bus
ered transmit and receive section.
" Result (R) Bus
The two address buses (PMA and DMA) share a single external " SPORTs can use an external serial clock or generate their own
address bus, allowing memory to be expanded off-chip, and the serial clock internally.
two data buses (PMD and DMD) share a single external data
" SPORTs have independent framing for the receive and trans-
bus. Byte memory space and I/O memory space also share the
mit sections. Sections run in a frameless mode or with frame
external buses.
synchronization signals internally or externally generated.
Program memory can store both instructions and data, permit- Frame sync signals are active high or inverted, with either of
ting the ADSP-2184 to fetch two operands in a single cycle, one two pulsewidths and timings.
from program memory and one from data memory. The ADSP-
" SPORTs support serial data word lengths from 3 to 16 bits
2184 can fetch an operand from program memory and the next
and provide optional A-law and µ -law companding according
instruction in the same cycle.
to CCITT recommendation G.711.
When configured in host mode, the ADSP-2184 has a 16-bit
" SPORT receive and transmit sections can generate unique
Internal DMA port (IDMA port) for connection to external
interrupts on completing a data word transfer.
systems. The IDMA port is made up of 16 data/address pins
" SPORTs can receive and transmit an entire circular buffer of
and five control pins. The IDMA port provides transparent,
data with only one overhead cycle per data word. An interrupt
direct access to the DSPs on-chip program and data RAM.
is generated after a data buffer transfer.
An interface to low cost byte-wide memory is provided by the
" SPORT0 has a multichannel interface to selectively receive
Byte DMA port (BDMA port). The BDMA port is bidirectional
and transmit a 24- or 32-word, time-division multiplexed,
and can directly address up to four megabytes of external RAM
serial bitstream.
or ROM for off-chip storage of program overlays or data tables.
" SPORT1 can be configured to have two external interrupts
The byte memory and I/O memory space interface supports
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
slow memories and I/O memory-mapped peripherals with
internally generated serial clock may still be used in this
programmable wait state generation. External devices can
configuration.
gain control of external buses with bus request/grant signals
(BR, BGH and BG). One execution mode (Go Mode) allows
PIN DESCRIPTIONS
the ADSP-2184 to continue running from on-chip memory.
The ADSP-2184 is available in a 100-lead LQFP package. In
Normal execution mode requires the processor to halt while
order to maintain maximum functionality and reduce package
buses are granted.
size and pin count, some serial port, programmable flag, inter-
The ADSP-2184 can respond to eleven interrupts. There are up
rupt and external bus pins have dual, multiplexed functionality.
to six external interrupts (one edge-sensitive, two level-sensitive
The external bus pins are configured during RESET only, while
and three configurable) and seven internal interrupts generated
serial port pins are software configurable during program execu-
by the timer, the serial ports (SPORTs), the Byte DMA port
tion. Flag and interrupt functionality is retained concurrently
and the power-down circuitry. There is also a master RESET
on multiplexed pins. In cases where pin functionality is re-
signal. The two serial ports provide a complete synchronous
configurable, the default state is shown in plain text; alternate
serial interface with optional companding in hardware and a
functionality is shown in italics.
REV. 0
 3
ADSP-2184
Common-Mode Pins Memory Interface Pins
The ADSP-2184 processor can be used in one of two modes:
# Input/
Full Memory Mode, which allows BDMA operation with full
Pin of Out-
external overlay memory and I/O capability, or Host Mode,
Name(s) Pins put Function
which allows IDMA operation with limited external addressing
RESET 1 I Processor Reset Input
capabilities. The operating mode is determined by the state of
BR 1 I Bus Request Input
the Mode C pin during RESET and cannot be changed while
BG 1 O Bus Grant Output
the processor is running.
BGH 1 O Bus Grant Hung Output
Full Memory Mode Pins (Mode C = 0)
DMS 1 O Data Memory Select Output
#
PMS 1 O Program Memory Select Output
of Input/
IOMS 1 O I/O Memory Select Output
Pin Name Pins Output Function
BMS 1 O Byte Memory Select Output
A13:0 14 O Address Output Pins for Pro-
CMS 1 O Combined Memory Select Output
gram, Data, Byte and I/O Spaces
RD 1 O Memory Read Enable Output
D23:0 24 I/O Data I/O Pins for Program,
WR 1 O Memory Write Enable Output
Data, Byte and I/O Spaces
IRQ2/ 1 I Edge- or Level-Sensitive
(8 MSBs Are Also Used as
Interrupt Request1
Byte Memory Addresses)
PF7 I/O Programmable I/O Pin
IRQL0/ 1 I Level-Sensitive Interrupt Requests1
Host Mode Pins (Mode C = 1)
PF5 I/O Programmable I/O Pin
#
IRQL1/ 1 I Level-Sensitive Interrupt Requests1
of Input/
PF6 I/O Programmable I/O Pin
Pin Name Pins Output Function
IRQE/ 1 I Edge-Sensitive Interrupt Requests1
IAD15:0 16 I/O IDMA Port Address/Data Bus
PF4 I/O Programmable I/O Pin
PF3 1 I/O Programmable I/O Pin A0 1 O Address Pin for External I/O,
Program, Data, or Byte Access
Mode C/ 1 I Mode Select Input Checked
only During RESET
D23:8 16 I/O Data I/O Pins for Program,
PF2 I/O Programmable I/O Pin During
Data Byte and I/O Spaces
Normal Operation
IWR 1 I IDMA Write Enable
Mode B/ 1 I Mode Select Input Checked
IRD 1 I IDMA Read Enable
only During RESET
IAL 1 I IDMA Address Latch Pin
PF1 I/O Programmable I/O Pin During
IS 1 I IDMA Select
Normal Operation
Mode A/ 1 I Mode Select Input Checked IACK 1 O IDMA Port Acknowledge
only During RESET
In Host Mode, external peripheral addresses can be decoded using the A0,
PF0 I/O Programmable I/O Pin During
BMS, CMS, PMS, DMS, and IOMS signals.
Normal Operation
Setting Memory Mode
CLKIN, XTAL 2 I Clock or Quartz Crystal Input
Memory Mode selection for the ADSP-2184 is made during
CLKOUT 1 O Processor Clock Output
chip reset through the use of the Mode C pin. This pin is multi-
SPORT0 5 I/O Serial Port I/O Pins
plexed with the DSP s PF2 pin, so care must be taken in how
SPORT1/ 5 I/O Serial Port I/O Pins
the mode selection is made. The two methods for selecting the
IRQ1:0 Edge- or Level-Sensitive Interrupts,
value of Mode C are passive and active.
FI, FO Flag In, Flag Out2
Passive configuration involves the use a pull-up or pull-down
PWD 1 I Power-Down Control Input
resistor connected to the Mode C pin. To minimize power
PWDACK 1 O Power-Down Control Output
consumption, or if the PF2 pin is to be used as an output in the
FL0, FL1, FL2 3 O Output Flags
DSP application, a weak pull-up or pull-down, on the order of
VDD and GND 16 I Power and Ground
100 k&! , can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as a
EZ-Port 9 I/O For Emulation Use
programmable flag output without undue strain on the processor s
NOTES
1
output driver. For minimum power consumption during
Interrupt/Flag pins retain both functions concurrently. If IMASK is set to
enable the corresponding interrupts, the DSP will vector to the appropriate
power-down, reconfigure PF2 to be an input, as the pull-up or
interrupt vector address when the pin is asserted, either by external devices or
pull-down will hold the pin in a known state, and will not switch.
set as a programmable flag.
2
SPORT configuration determined by the DSP System Control Register. Soft- Active configuration involves the use of a three-stateable exter-
ware configurable.
nal driver connected to the Mode C pin. A driver s output en-
able should be connected to the DSP s RESET signal such that
it only drives the PF2 pin when RESET is active (low). After
RESET is deasserted, the driver should three-state, thus allow-
ing full use of the PF2 pin as either an input or output.
REV. 0
 4
ADSP-2184
To minimize power consumption during power-down, configure The IFC register is a write-only register used to force and clear
the programmable flag as an output when connected to a three- interrupts.
stated buffer. This ensures that the pin will be held at a constant
On-chip stacks preserve the processor status and are automati-
level and not oscillate should the three-state driver s level hover
cally maintained during interrupt handling. The stacks are twelve
around the logic switching point.
levels deep to allow interrupt, loop and subroutine nesting.
Interrupts
The following instructions allow global enable or disable servic-
The interrupt controller allows the processor to respond to the
ing of the interrupts (including power-down), regardless of the
eleven possible interrupts and reset with minimum overhead.
state of IMASK. Disabling the interrupts does not affect serial
The ADSP-2184 provides four dedicated external interrupt
port autobuffering or DMA.
input pins, IRQ2, IRQL0, IRQL1 and IRQE (shared with the
ENA INTS;
PF7:4 pins). In addition, SPORT1 may be reconfigured for
IRQ0, IRQ1, FLAG_IN and FLAG_OUT, for a total of six
DIS INTS;
external interrupts. The ADSP-2184 also supports internal
When the processor is reset, interrupt servicing is enabled.
interrupts from the timer, the byte DMA port, the two serial
ports, software and the power-down control circuit. The inter-
LOW POWER OPERATION
rupt levels are internally prioritized and individually maskable
The ADSP-2184 has three low power modes that significantly
(except power-down and RESET). The IRQ2, IRQ0 and IRQ1
reduce the power dissipation when the device operates under
input pins can be programmed to be either level- or edge-sensitive.
standby conditions. These modes are:
IRQL0 and IRQL1 are level-sensitive and IRQE is edge-sensitive.
" Power-Down
The priorities and vector addresses of all interrupts are shown in
Table I.
" Idle
" Slow Idle
Table I. Interrupt Priority & Interrupt Vector Addresses
The CLKOUT pin may also be disabled to reduce external
Source Of Interrupt Interrupt Vector Address (Hex)
power dissipation.
Reset (or Power-Up with
Power-Down
PUCR = 1) 0000 (Highest Priority)
The ADSP-2184 processor has a low power feature that lets the
processor enter a very low power dormant state through hard-
Power-Down (Nonmaskable) 002C
ware or software control. Following is a brief list of power-down
IRQ2 0004
features. Refer to the ADSP-2100 Family User s Manual, Third
IRQL1 0008
Edition,  System Interface chapter, for detailed information
IRQL0 000C
about the power-down feature.
SPORT0 Transmit 0010
" Quick recovery from power-down. The processor begins
SPORT0 Receive 0014
executing instructions in as few as 200 CLKIN cycles.
IRQE 0018
" Support for an externally generated TTL or CMOS proces-
BDMA Interrupt 001C
sor clock. The external clock can continue running during
SPORT1 Transmit or IRQ1 0020
power-down without affecting the lowest power rating and
SPORT1 Receive or IRQ0 0024 200 CLKIN cycle recovery.
Timer 0028 (Lowest Priority)
" Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits approxi-
Interrupt routines can either be nested, with higher priority
mately 4096 CLKIN cycles for the crystal oscillator to start
interrupts taking precedence, or processed sequentially. Inter-
or stabilize), and letting the oscillator run to allow 200 CLKIN
rupts can be masked or unmasked with the IMASK register.
cycle start-up.
Individual interrupt requests are logically ANDed with the bits
" Power-down is initiated by either the power-down pin (PWD)
in IMASK; the highest priority unmasked interrupt is then
or the software power-down force bit.
selected. The power-down interrupt is nonmaskable.
" Interrupt support allows an unlimited number of instructions
The ADSP-2184 masks all interrupts for one instruction cycle
to be executed before optionally powering down. The power-
following the execution of an instruction that modifies the
down interrupt also can be used as a nonmaskable, edge-
IMASK register. This does not affect serial port autobuffering
sensitive interrupt.
or DMA transfers.
" Context clear/save control allows the processor to continue
The interrupt control register, ICNTL, controls interrupt nest-
where it left off or start with a clean context when leaving the
ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
power-down state.
be either edge- or level-sensitive. The IRQE pin is an external
" The RESET pin also can be used to terminate power-down.
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
" Power-down acknowledge pin indicates when the processor
has entered power-down.
REV. 0
 5
ADSP-2184
Idle
FULL MEMORY MODE
When the ADSP-2184 is in the Idle Mode, the processor waits
ADSP-2184
indefinitely in a low power state until an interrupt occurs. When
CLKIN
1/2x CLOCK 14 A13-0
OR ADDR13-0
an unmasked interrupt occurs, it is serviced; execution then XTAL
CRYSTAL
D23-16 A0-A21
continues with the instruction following the IDLE instruction. FL0-2
BYTE
24 D15-8
PF3
MEMORY
DATA23-0 DATA
In Idle mode IDMA, BDMA and autobuffer cycle steals still
IRQ2/PF7
IRQE/PF4
occur.
BMS CS
IRQL0/PF5
IRQL1/PF6 A10-0
Slow Idle
ADDR
MODE C/PF2 D23-8
I/O SPACE
The IDLE instruction is enhanced on the ADSP-2184 to let the
MODE B/PF1 DATA
(PERIPHERALS)
MODE A/PF0
processor s internal clock signal be slowed, further reducing
2048 LOCATIONS
IOMS CS
power consumption. The reduced clock frequency, a program-
A13-0
SPORT1 ADDR
mable fraction of the normal clock rate, is specified by a select-
OVERLAY
D23-0
SCLK1
MEMORY
able divisor given in the IDLE instruction. The format of the RFS1 OR IRQ0 DATA
SERIAL
TFS1 OR IRQ1
TWO 8K
DEVICE
CS
DT1 OR FO
instruction is PMS PM SEGMENTS
DR1 OR FI
DMS
TWO 8K
CMS
IDLE (n); SPORT0 DM SEGMENTS
SCLK0
BR
RFS0
BG
SERIAL
where n = 16, 32, 64 or 128. This instruction keeps the proces-
TFS0
DEVICE BGH
DT0
sor fully functional, but operating at the slower clock rate. While
DR0 PWD
PWDACK
it is in this state, the processor s other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
HOST MEMORY MODE
same ratio. The default form of the instruction, when no clock
ADSP-2184
divisor is given, is the standard IDLE instruction.
1/2x CLOCK CLKIN
1
When the IDLE (n) instruction is used, it effectively slows down
OR ADDR0
CRYSTAL XTAL
the processor s internal clock and thus its response time to in-
FL0-2
PF3 16
coming interrupts. The one-cycle response time of the standard
DATA23-8
IRQ2/PF7
idle state is increased by n, the clock divisor. When an enabled
IRQE/PF4
BMS
IRQL0/PF5
interrupt is received, the ADSP-2184 will remain in the idle
IRQL1/PF6
state for up to a maximum of n processor cycles (n = 16, 32, 64
MODE C/PF2
MODE B/PF1
or 128) before resuming normal operation.
MODE A/PF0
When the IDLE (n) instruction is used in systems that have an
IOMS
SPORT1
SCLK1
externally generated serial clock (SCLK), the serial clock rate
RFS1 OR IRQ0
SERIAL
TFS1 OR IRQ1
DEVICE
may be faster than the processor s reduced internal clock rate.
DT1 OR FO
DR1 OR FI
Under these conditions, interrupts must not be generated at a
SPORT0 PMS
faster rate than can be serviced, due to the additional time the
SCLK0 DMS
RFS0
CMS
SERIAL
processor takes to come out of the idle state (a maximum of n
TFS0
DEVICE
DT0
BR
processor cycles).
DR0
BG
BGH
IDMA PORT
PWD
IRD/D6
SYSTEM INTERFACE PWDACK
SYSTEM IWR/D7
INTERFACE IS/D4
Figure 2 shows typical basic system configurations with the
OR IAL/D5
CONTROLLER IACK/D3
16
ADSP-2184, two serial devices, a byte-wide EPROM and optional
IAD15-0
external program and data overlay memories (mode selectable).
Programmable wait state generation allows the processor to
Figure 2. Basic System Configuration
connect easily to slow peripheral devices. The ADSP-2184 also
provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode
allows access to the full external data bus, but limits addressing
to a single address bit (A0). Additional system peripherals can
be added in this mode through the use of external hardware to
generate and latch address signals.
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 6
ADSP-2184
Clock Signals The master reset sets all internal stack pointers to the empty
The ADSP-2184 can be clocked by either a crystal or a TTL- stack condition, masks all interrupts and clears the MSTAT
compatible clock signal. register. When RESET is released, if there is no pending bus
request and the chip is configured for booting, the boot-loading
The CLKIN input cannot be halted, changed during operation
sequence is performed. The first instruction is fetched from
or operated below the specified frequency during normal opera-
on-chip program memory location 0x0000 once boot loading
tion. The only exception is while the processor is in the power-
completes. In an EZ-ICE-compatible system RESET and
down state. For additional information, refer to Chapter 9,
ERESET have the same functionality. For complete informa-
ADSP-2100 Family User s Manual, Third Edition, for detailed
tion, see Designing an EZ-ICE-Compatible Systems section.
information on this power-down feature.
If an external clock is used, it should be a TTL-compatible
MEMORY ARCHITECTURE
signal running at half the instruction rate. The signal is con- The ADSP-2184 provides a variety of memory and peripheral
nected to the processor s CLKIN input. When an external clock
interface options. The key functional groups are Program Memory,
is used, the XTAL input must be left unconnected.
Data Memory, Byte Memory and I/O.
The ADSP-2184 uses an input clock with a frequency equal to
Program Memory (Full Memory Mode) is a 24-bit-wide space
half the instruction rate; a 20.00 MHz input clock yields a 25 ns
for storing both instruction opcodes and data. The ADSP-2184
processor cycle (which is equivalent to 40 MHz). Normally,
has 4K words of Program Memory RAM on chip, and the capabil-
instructions are executed in a single processor cycle. All device
ity of accessing up to two 8K external memory overlay spaces using
timing is relative to the internal instruction clock rate, which is
the external data bus. Both an instruction opcode and a data value
indicated by the CLKOUT signal when enabled.
can be read from on-chip program memory in a single cycle.
Because the ADSP-2184 includes an on-chip oscillator circuit,
Data Memory (Full Memory Mode) is a 16-bit-wide space
an external crystal may be used. The crystal should be con-
used for the storage of data variables and for memory-mapped
nected across the CLKIN and XTAL pins, with two capacitors
control registers. The ADSP-2184 has 4K words on Data
connected as shown in Figure 3. Capacitor values are dependent
Memory RAM on chip. Support also exists for up to two 8K
on crystal type and should be specified by the crystal manufac- external memory overlay spaces through the external data bus.
turer. A parallel-resonant, fundamental frequency, microproces-
Byte Memory (Full Memory Mode) provides access to an
sor-grade crystal should be used.
8-bit wide memory space through the Byte DMA (BDMA) port.
A clock output (CLKOUT) signal is generated by the proces- The Byte Memory interface provides access to 4 MBytes of
sor at the processor s cycle rate. This can be enabled and
memory by utilizing eight data lines as additional address lines.
disabled by the CLKODIS bit in the SPORT0 Autobuffer
This gives the BDMA Port an effective 22-bit address range. On
Control Register.
power-up, the DSP can automatically load bootstrap code from
byte memory.
I/O Space (Full Memory Mode) allows access to 2048 loca-
tions of 16-bit-wide data. It is intended to be used to communi-
XTAL
CLKIN CLKOUT
cate with parallel peripheral devices such as data converters and
external registers or latches.
DSP
Program Memory
The ADSP-2184 contains 4K × 24 of on-chip program RAM.
The on-chip program memory is designed to allow up to two
Figure 3. External Crystal Connections
accesses each cycle so that all operations can complete in a
Reset
single cycle. In addition, the ADSP-2184 allows the use of 8K
The RESET signal initiates a master reset of the ADSP-2184.
external memory overlays.
The RESET signal must be asserted during the power-up
The program memory space organization is controlled by the
sequence to assure proper initialization. RESET during initial
Mode B pin and the PMOVLAY register. Normally, the ADSP-
power-up must be held long enough to allow the internal clock
2184 is configured with Mode B = 0 and program memory
to stabilize. If RESET is activated any time after power-up, the
organized as shown in Figure 4.
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for PROGRAM MEMORY ADDRESS
the crystal oscillator circuit to stabilize after a valid VDD is
0x3FFF
EXTERNAL 8K
applied to the processor, and for the internal phase-locked loop
(PMOVLAY = 1 or 2,
MODE B = 0)
(PLL) to lock onto the specific crystal frequency. A minimum of
0x2000
2000 CLKIN cycles ensures that the PLL has locked, but does
0x1FFF
not include the crystal oscillator start-up time. During this RESERVED
MEMORY
power-up sequence the RESET signal should be held low. On
RANGE
0x1000
any subsequent resets, the RESET signal must meet the mini-
0x0FFF
mum pulsewidth specification, tRSP.
4K INTERNAL
The RESET input contains some hysteresis; however, if you use
0x0000
an RC circuit is used to generate your RESET signal, the use of
an external Schmidt trigger is recommended.
Figure 4. Program Memory (Mode B = 0)
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ADSP-2184
When PMOVLAY is set to 1 or 2, external accesses occur at There are 4K words of memory accessible internally when the
addresses 0x2000 through 0x3FFF. The external address is DMOVLAY register is set to 0. When DMOVLAY is set to 1 or
generated as shown in Table II. 2, external accesses occur at addresses 0x0000 through 0x1FFF.
Table II. The external address is generated as shown in Table III.
Table III.
PMOVLAY Memory A13 A12:0
DMOVLAY Memory A13 A12:0
0 Internal Not Applicable Not Applicable
0 Internal Not Applicable Not Applicable
1 External 13 LSBs of Address
Overlay 1 0 Between 0x2000
1 External 13 LSBs of Address
and 0x3FFF
Overlay 1 0 Between 0x0000
and 0x1FFF
2 External 13 LSBs of Address
Overlay 2 1 Between 0x2000
2 External 13 LSBs of Address
and 0x3FFF
Overlay 2 1 Between 0x0000
and 0x1FFF
NOTE: Addresses 0x2000 through 0x3FFF should not be accessed when
PMOVLAY = 0.
This organization allows for two external 8K overlays using only
This organization provides for two external 8K overlay segments
the normal 14 address bits. All internal accesses complete in one
using only the normal 14 address bits, which allows for simple
cycle. Accesses to external memory are timed using the wait
program overlays using one of the two external segments in
states specified by the DWAIT register.
place of the on-chip memory. Care must be taken in using this
I/O Space (Full Memory Mode)
overlay space in that the processor core (i.e., the sequencer)
The ADSP-2184 supports an additional external memory space
does not take into account the PMOVLAY register value. For
called I/O space. This space is designed to support simple con-
example, if a loop operation is occurring on one of the external
nections to peripherals or to bus interface ASIC data registers.
overlays and the program changes to another external overlay or
I/O space supports 2048 locations. The lower eleven bits of the
internal memory, an incorrect loop operation could occur. In
external address bus are used; the upper three bits are unde-
addition, care must be taken in interrupt service routines as the
fined. Two instructions were added to the core ADSP-2100
overlay registers are not automatically saved and restored on the
Family instruction set to read from and write to I/O memory
processor mode stack.
space. The I/O space also has four dedicated three-bit wait state
When Mode B = 1, booting is disabled and overlay memory is
registers, IOWAIT0-3, that specify up to seven wait states to be
disabled the 4K internal PM cannot be accessed with MODE
automatically generated for each of four regions. The wait states
B = 1. Figure 5 shows the memory map in this configuration.
act on address ranges as shown in Table IV.
PROGRAM MEMORY ADDRESS
0x3FFF
Table IV.
RESERVED
Address Range Wait State Register
0x2000
0x000 0x1FF IOWAIT0
0x1FFF
0x200 0x3FF IOWAIT1
8K EXTERNAL
0x400 0x5FF IOWAIT2
0x600 0x7FF IOWAIT3
0x0000
Figure 5. Program Memory (Mode B = 1)
Composite Memory Select (CMS)
Data Memory The ADSP-2184 has a programmable memory select signal that
The ADSP-2184 has 4K 16-bit words of internal data memory. In is useful for generating memory select signals for memories
addition, the ADSP-2184 allows the use of 8K external memory mapped to more than one space. The CMS signal is generated
overlays. Figure 6 shows the organization of the data memory. to have the same timing as each of the individual memory select
DATA MEMORY ADDRESS signals (PMS, DMS, BMS, IOMS), but can combine their
0x3FFF functionality.
32 MEMORY
MAPPED REGISTERS
Each bit in the CMSSEL register, when set, causes the CMS
0x3FEO
signal to be asserted when the selected memory select is as-
0x3FDF
4064
serted. For example, to use a 32K word memory to act as both
RESERVED
WORDS
0x3000
program and data memory, set the PMS and DMS bits in the
0x2FFF
CMSSEL register and use the CMS pin to drive the chip select
INTERNAL
4K WORDS
of the memory and use either DMS or PMS as the additional
0x2000
address bit.
0x1FFF
EXTERNAL 8K
The CMS pin functions as the other memory select signals, with
(DMOVLAY = 1, 2)
0x0000
the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
Figure 6. Data Memory
selected memory select signal. All enable bits, except the BMS
bit, default to 1 at reset.
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ADSP-2184
Byte Memory When the BWCOUNT register is written with a nonzero value,
The byte memory space is a bidirectional, 8-bit-wide, external the BDMA circuit starts executing byte memory accesses with
memory space used to store programs and data. Byte memory is wait states set by BMWAIT. These accesses continue until the
accessed using the BDMA feature. The byte memory space count reaches zero. When enough accesses have occurred to
consists of 256 pages, each of which is 16K × 8. create a destination word, it is transferred to or from on-chip
memory. The transfer takes one DSP cycle. DSP accesses to
The byte memory space on the ADSP-2184 supports read and
external memory have priority over BDMA byte memory
write operations as well as four different data formats. The byte
accesses.
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address. The BDMA Context Reset bit (BCR) controls whether the
This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be processor is held off while the BDMA accesses are occurring.
used without glue logic. All byte memory accesses are timed by Setting the BCR bit to 0 allows the processor to continue opera-
the BMWAIT register. tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
Byte Memory DMA (BDMA, Full Memory Mode)
context of the processor and start execution at address 0 when
The Byte memory DMA controller allows loading and storing of
the BDMA accesses have completed.
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space Internal Memory DMA Port (IDMA Port; Host Memory Mode)
while the processor is operating normally and steals only one The IDMA Port provides an efficient means of communication
DSP cycle per 8-, 16- or 24-bit word transferred. between a host system and the ADSP-2184. The port is used to
access the on-chip program memory and data memory of the
The BDMA circuit supports four different data formats that are
DSP with only one DSP cycle per word overhead. The IDMA
selected by the BTYPE register field. The appropriate number
port cannot, however, be used to write to the DSP s memory-
of 8-bit accesses is done from the byte memory space to build
mapped control registers.
the word size selected. Table V shows the data formats sup-
ported by the BDMA circuit. The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is com-
Table V. pletely asynchronous and can be written to while the ADSP-
2184 is operating at full speed.
Internal
The DSP memory address is latched and then automatically
BTYPE Memory Space Word Size Alignment
incremented after each IDMA transaction. An external device
00 Program Memory 24 Full Word
can therefore access a block of sequentially addressed memory
01 Data Memory 16 Full Word
by specifying only the starting address of the block. This in-
10 Data Memory 8 MSBs
creases throughput as the address does not have to be sent for
11 Data Memory 8 LSBs
each memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Unused bits in the 8-bit data memory formats are filled with 0s.
Address Latch cycle. When the acknowledge is asserted, a 14-bit
The BIAD register field is used to specify the starting address for
address and 1-bit destination type can be driven onto the bus by
the on-chip memory involved with the transfer. The 14-bit BEAD
an external device. The address specifies an on-chip memory
register specifies the starting address for the external byte memory
location, the destination type specifies whether it is a DM or
space. The 8-bit BMPAGE register specifies the starting page for
PM access. The falling edge of the IDMA address latch signal
the external byte memory space. The BDIR register field selects
(IAL) or the missing edge of the IDMA select signal (IS) latches
the direction of the transfer. The 14-bit BWCOUNT register
this value into the IDMAA register.
specifies the number of DSP words to transfer and initiates the
Once the address is stored, data can then either be read from or
BDMA circuit transfers.
written to the ADSP-2184 s on-chip memory. Asserting the
BDMA accesses can cross page boundaries during sequential
select line (IS) and the appropriate read or write line (IRD and
addressing. A BDMA interrupt is generated on the completion
IWR respectively) signals the ADSP-2184 that a particular
of the number of transfers specified by the BWCOUNT register.
transaction is required. In either case, there is a one-processor-
The BWCOUNT register is updated after each transfer so it can
cycle delay for synchronization. The memory access consumes
be used to check the status of the transfers. When it reaches
one additional processor cycle.
zero, the transfers have finished and a BDMA interrupt is gener-
Once an access has occurred, the latched address is automati-
ated. The BMPAGE and BEAD registers must not be accessed
cally incremented and another access can occur.
by the DSP during BDMA operations.
Through the IDMAA register, the DSP can also specify the
The source or destination of a BDMA transfer will always be
starting address and data format for DMA operation.
on-chip program or data memory, regardless of the values of
Mode B, PMOVLAY or DMOVLAY.
REV. 0
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ADSP-2184
Bootstrap Loading (Booting) The IDLE instruction can also be used to allow the processor to
The ADSP-2184 has two mechanisms to allow automatic load- hold off execution while booting continues through the BDMA
ing of the internal program memory after reset. The method for interface. For BDMA accesses while in Host Mode, the ad-
booting is controlled by the Mode A, B and C configuration bits dresses to boot memory must be constructed externally to the
as shown in Table VI. These four states can be compressed into ADSP-2184. The only memory address bit provided by the
two-state bits by allowing an IDMA boot with Mode C = 1. processor is A0.
However, three bits are used to ensure future compatibility with
IDMA Port Booting
parts containing internal program memory ROM.
The ADSP-2184 can also boot programs through its Internal
BDMA Booting DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the
When the MODE pins specify BDMA booting, the ADSP-2184 ADSP-2184 boots from the IDMA port. The IDMA feature can
initiates a BDMA boot sequence when RESET is released. load as much on-chip memory as desired. Program execution is
held off until on-chip program memory location 0 is written to.
Table VI. Boot Summary Table
Bus Request and Bus Grant
The ADSP-2184 can relinquish control of the data and address
MODE C MODE B MODE A Booting Method
buses to an external device. When the external device requires
0 0 0 BDMA feature is used to load
access to memory, it asserts the bus request (BR) signal. If the
the first 32 program memory
ADSP-2184 is not performing an external memory access, it
words from the byte memory
responds to the active BR input in the following processor cycle
space. Program execution is
by:
held off until all 32 words have
" Three-stating the data and address buses and the PMS, DMS,
been loaded. Chip is config-
BMS, CMS, IOMS, RD, WR output drivers,
ured in Full Memory Mode.
" Asserting the bus grant (BG) signal, and
0 1 0 No Automatic boot operations
" Halting program execution.
occur. Program execution
If Go Mode is enabled, the ADSP-2184 will not halt program
starts at external memory
execution until it encounters an instruction that requires an
location 0. Chip is configured
external memory access.
in Full Memory Mode. BDMA
can still be used but the pro-
If the ADSP-2184 is performing an external memory access
cessor does not automatically
when the external device asserts the BR signal, it will not three-
use or wait for these operations.
state the memory interfaces or assert the BG signal until the
processor cycle after the access completes. The instruction does
1 0 0 BDMA feature is used to load
not need to be completed when the bus is granted. If a single
the first 32 program memory
instruction requires two external memory accesses, the bus will
words from the byte memory
be granted between the two accesses.
space. Program execution is
held off until all 32 words have When the BR signal is released, the processor releases the BG
been loaded. Chip is config- signal, reenables the output drivers and continues program
ured in Host Mode. Additional execution from the point at which it stopped.
interface hardware is required.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
1 0 1 IDMA feature is used to load
any internal memory as de- The BGH pin is asserted when the ADSP-2184 is ready to
sired. Program execution is
execute an instruction but is stopped because the external bus is
held off until internal program
already granted to another device. The other device can release
memory location 0 is written
the bus by deasserting bus request. Once the bus is released, the
to. Chip is configured in Host
ADSP-2184 deasserts BG and BGH and executes the external
Mode.
memory access.
Flag I/O Pins
The BDMA interface is set up during reset to the following de-
The ADSP-2184 has eight general purpose programmable input/
faults when BDMA booting is specified: the BDIR, BMPAGE,
output flag pins. They are controlled by two memory mapped
BIAD and BEAD registers are set to 0; the BTYPE register is
registers. The PFTYPE register determines the direction,
set to 0 to specify program memory 24-bit words; and the
1 = output and 0 = input. The PFDATA register is used to read
BWCOUNT register is set to 32. This causes 32 words of on-
and write the values on the pins. Data being read from a pin
chip program memory to be loaded from byte memory. These
configured as an input is synchronized to the ADSP-2184 s
32 words are used to set up the BDMA to load in the remaining
clock. Bits that are programmed as outputs will read the value
program code. The BCR bit is also set to 1, which causes pro-
being output. The PF pins default to input during reset.
gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
REV. 0
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ADSP-2184
In addition to the programmable flags, the ADSP-2184 has five
fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and
ERESET
FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1. RESET
Note: Pins PF0, PF1 and PF2 are also used for device configu-
ration during reset.
ADSP-2184
INSTRUCTION SET DESCRIPTION
The ADSP-2184 assembly language instruction set has an alge-
1k
MODE A/PFO
braic syntax that was designed for ease of coding and readabil-
ity. The assembly language, which takes full advantage of the
processor s unique architecture, offers the following benefits:
" The algebraic syntax eliminates the need to remember cryptic
PROGRAMMABLE I/O
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
Figure 7.
equation.
See the ADSP-2100 Family EZ-Tools data sheet for complete
" Every instruction assembles into a single, 24-bit word that
information on ICE products.
can execute in a single instruction cycle.
The ICE-Port interface consists of the following ADSP-2184
" The syntax is a superset ADSP-2100 Family assembly lan-
pins:
guage and is completely source and object code compatible
with other family members. Programs may need to be relo- EBR EBG ERESET
cated to utilize on-chip memory and conform to the ADSP- EMS EINT ECLK
2184 s interrupt vector and reset vector map.
ELIN ELOUT EE
" Sixteen condition codes are available. For conditional jump,
These ADSP-2184 pins must be connected only to the EZ-ICE
call, return or arithmetic instructions, the condition can be
connector in the target system. These pins have no function
checked and the operation executed in the same instruction
except during emulation, and do not require pull-up or
cycle.
pull-down resistors. The traces for these signals between the
" Multifunction instructions allow parallel execution of an
ADSP-2184 and the connector must be kept as short as pos-
arithmetic instruction with up to two fetches or one write to
sible, no longer than three inches.
processor memory space during a single instruction cycle.
The following pins are also used by the EZ-ICE:
BR BG
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
RESET GND
The ADSP-2184 has on-chip emulation support and an
ICE-Port, a special set of pins that interface to the EZ-ICE. These
The EZ-ICE uses the EE (emulator enable) signal to take con-
features allow in-circuit emulation without replacing the target
trol of the ADSP-2184 in the target system. This causes the
system processor by using only a 14-pin connection from the
processor to use its ERESET, EBR and EBG pins instead of
target system to the EZ-ICE. Target systems must have a 14-pin
the RESET, BR and BG pins. The BG output is three-stated.
connector to accept the EZ-ICE s in-circuit probe, a 14-pin plug.
These signals do not need to be jumper-isolated in your system.
Issuing the chip reset command during emulation causes the
The EZ-ICE connects to your target system via a ribbon cable
DSP to perform a full chip reset, including a reset of its memory
and a 14-pin female plug. The female plug is plugged onto the
mode. Therefore, it is vital that the mode pins are set correctly
14-pin connector (a pin strip header) on the target board.
PRIOR to issuing a chip reset command from the emulator user
Target Board Connector for EZ-ICE Probe
interface.
The EZ-ICE connector (a standard pin strip header) is shown in
If using a passive method of maintaining mode information (as
Figure 8. You must add this connector to your target board
discussed in Setting Memory Modes), it does not matter that
design if you intend to use the EZ-ICE. Be sure to allow enough
the mode information is latched by an emulator reset. However,
room in your system to fit the EZ-ICE probe onto the 14-pin
if using the RESET pin as a method of setting the value of the
connector.
mode pins, the effects of an emulator reset must be taken into
consideration.
One method of ensuring that the values located on the mode
pins is the one that is desired to construct a circuit like the one
shown in Figure 7. This circuit will force the value located on
the Mode A pin to Logic Low, regardless if it latched via the
RESET or ERESET pin.
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ADSP-2184
Note: If your target does not meet the worst case chip specifica-
1 2
tions for memory access parameters, you may not be able to
BG
GND
emulate your circuitry at the desired CLKIN frequency. Depend-
3 4
ing on the severity of the specification violation, you may have
EBG
BR
trouble manufacturing your system as DSP components statisti-
5 6
cally vary in switching characteristics and timing requirements
EBR EINT
within published limits.
7 8
KEY (NO PIN)
ELIN
Restriction: All memory strobe signals on the ADSP-2184 (RD,
WR, PMS, DMS, BMS, CMS and IOMS) used in your target
9 10
ELOUT ECLK
system must have 10 k&! pull-up resistors connected when the
EZ-ICE is being used. The pull-up resistors are necessary
11 12
EMS
EE
because there are no internal pull-ups to guarantee their state
13 14 during prolonged three-state conditions resulting from typical
RESET ERESET
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
TOP VIEW
Target System Interface Signals
Figure 8. Target Board Connector for EZ-ICE
When the EZ-ICE board is installed, the performance on some
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
system signals change. Design your system to be compatible
tion you must remove Pin 7 from the header. The pins must
with the following system interface signal changes introduced by
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
the EZ-ICE board:
ing should be 0.1 × 0.1 inches. The pin strip header must have
" EZ-ICE emulation introduces an 8 ns propagation delay
at least 0.15-inch clearance on all sides to accept the EZ-ICE
between your target circuitry and the DSP on the RESET
probe plug. Pin strip headers are available from vendors such as
signal.
3M, McKenzie and Samtec.
" EZ-ICE emulation introduces an 8 ns propagation delay
Target Memory Interface
between your target circuitry and the DSP on the BR signal.
For your target system to be compatible with the EZ-ICE emu-
" EZ-ICE emulation ignores RESET and BR when single-
lator, it must comply with the memory interface guidelines listed
stepping.
below.
" EZ-ICE emulation ignores RESET and BR when in Emulator
PM, DM, BM, IOM, and CM
Space (DSP halted).
Design a Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM) and Composite Memory
" EZ-ICE emulation ignores the state of target BR in certain
(CM) external interfaces to comply with worst case device tim-
modes. As a result, the target system may take control of the
ing requirements and switching characteristics as specified in
DSP s external memory bus only if bus grant (BG) is asserted
this DSP s data sheet. The performance of the EZ-ICE may ap-
by the EZ-ICE board s DSP.
proach published worst case specifications for some memory
access timing requirements and switching characteristics.
REV. 0
 12
ADSP-2184
SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
B Grade
Parameter Min Max Unit
VDD 4.5 5.5 V
TAMB  40 +85 ° C
ELECTRICAL CHARACTERISTICS
B Grade
Parameter Test Conditions Min Typ Max Unit
VIH Hi-Level Input Voltage1, 2 @ VDD = max 2.0 V
VIH Hi-Level CLKIN Voltage @ VDD = max 2.2 V
VIL Lo-Level Input Voltage1, 3 @ VDD = min 0.8 V
VOH Hi-Level Output Voltage1, 4, 5 @ VDD = min
IOH =  0.5 mA 2.4 V
@ VDD = min
IOH =  100 µ A6 VDD  0.3 V
VOL Lo-Level Output Voltage1, 4, 5 @ VDD = min
IOL = 2 mA 0.4 V
IIH Hi-Level Input Current3 @ VDD = max
VIN = VDD max 10 µ A
IIL Lo-Level Input Current3 @ VDD = max
VIN = 0 V 10 µ A
IOZH Three-State Leakage Current7 @ VDD = max
VIN = VDD max8 10 µ A
IOZL Three-State Leakage Current7 @ VDD = max
VIN = 0 V8, tCK = 25 ns 10 µ A
IDD Supply Current (Idle)9 @ VDD = 5.0 14 mA
IDD Supply Current (Dynamic)10, 11 @ VDD = 5.0
TAMB = +25° C
tCK = 25 ns 60 mA
CI Input Pin Capacitance3, 6, 12 @ VIN = 2.5 V,
fIN = 1.0 MHz, 8 pF
TAMB = +25° C
CO Output Pin Capacitance6, 7, 12, 13 @ VIN = 2.5 V,
fIN = 1.0 MHz,
TAMB = +25° C8 pF
NOTES
1
Bidirectional pins: D0 D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1 A13, PF0 PF7.
2
Input only pins: RESET, BR, DR0, DR1, PWD.
3
Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4
Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH.
5
Although specified for TTL outputs, all ADSP-2184 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.
6
Guaranteed but not tested.
7
Three-statable pins: A0 A13, D0 D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, PF0 PF7.
8
0 V on BR.
9
Idle refers to ADSP-2184 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V or GND.
DD
10
IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2
and type 6, and 20% are idle instructions.
11
VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
12
Applies to LQFP package type.
13
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
REV. 0  13
ADSP-2184
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .  0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . .  0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . .  0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . .  40° C to +85° C
Storage Temperature Range . . . . . . . . . . . .  65° C to +150° C
Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . +280° C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
WARNING!
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2184 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.
TIMING PARAMETERS
GENERAL NOTES MEMORY TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to The table below shows common memory device specifications
derive parameters from the addition or subtraction of others. and the corresponding ADSP-2184 timing parameters, for your
While addition or subtraction would yield meaningful results for convenience.
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
Memory ADSP-2184 Timing
meaningfully add up parameters to derive longer times.
Device Timing Parameter
Specification Parameter Definition
TIMING NOTES
Address Setup to tASW A0 A13, xMS Setup
Switching characteristics specify how the processor changes its
Write Start before WR Low
signals. You have no control over this timing circuitry external
to the processor must be designed for compatibility with these Address Setup to tAW A0 A13, xMS Setup
signal characteristics. Switching characteristics tell you what the Write End before WR Deasserted
processor will do in a given circumstance. You can also use
Address Hold Time tWRA A0 A13, xMS Hold before
switching characteristics to ensure that any timing requirement
WR Low
of a device connected to the processor (such as memory) is
Data Setup Time tDW Data Setup before WR
satisfied.
High
Timing requirements apply to signals that are controlled by
Data Hold Time tDH Data Hold after WR High
circuitry external to the processor, such as the data input for a
OE to Data Valid tRDD RD Low to Data Valid
read operation. Timing requirements guarantee that the proces-
sor operates correctly with other devices. Address Access Time tAA A0 A13, xMS to Data
Valid
xMS = PMS, DMS, BMS, CMS, IOMS.
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS
tCK is defined as 0.5 tCKI. The ADSP-2184 uses an input clock
with a frequency equal to half the instruction rate: a 20 MHz
input clock (which is equivalent to 50 ns) yields a 25 ns proces-
sor cycle (equivalent to 40 MHz). tCK values within the range of
0.5 tCKI period should be substituted for all relevant timing para-
meters to obtain the specification value.
Example: tCKH = 0.5 tCK  7 ns = 0.5 (25 ns)  7 ns = 5.5 ns
REV. 0
 14
ADSP-2184
TIMING PARAMETERS
Parameter Min Max Unit
Clock Signals and Reset
Timing Requirements:
tCKI CLKIN Period 50 150 ns
tCKIL CLKIN Width Low 20 ns
tCKIH CLKIN Width High 20 ns
Switching Characteristics:
tCKL CLKOUT Width Low 0.5 tCK  7 ns
tCKH CLKOUT Width High 0.5 tCK  7 ns
tCKOH CLKIN High to CLKOUT High 0 20 ns
Control Signals
Timing Requirements:
tRSP RESET Width Low1 5 tCK ns
tMS Mode Setup before RESET High 2 ns
tMH Mode Setup after RESET High 5 ns
NOTES
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
PF(2:0)*
tMS tMH
RESET
*PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A
Figure 9. Clock Signals
REV. 0
 15
ADSP-2184
TIMING PARAMETERS
Parameter Min Max Unit
Interrupts and Flag
Timing Requirements:
tIFS IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4 0.25 tCK + 15 ns
tIFH IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4 0.25 tCK ns
Switching Characteristics:
tFOH Flag Output Hold after CLKOUT Low5 0.25 tCK  7 ns
tFOD Flag Output Delay from CLKOUT Low5 0.5 tCK + 6 ns
NOTES
1
If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the
following cycle. (Refer to  Interrupt Controller Operation in the Program Control chapter of the ADSP-2100 Family User s Manual, Third Edition, for further information
on interrupt servicing.)
2
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag outputs = PFx, FL0, FL1, FL2, Flag_out.
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
PFx
tIFS
Figure 10.#$ Interrupts and Flags
REV. 0
 16
ADSP-2184
Parameter Min Max Unit
Bus Request Bus Grant
Timing Requirements:
tBH BR Hold after CLKOUT High1 0.25 tCK + 2 ns
tBS BR Setup before CLKOUT Low1 0.25 tCK + 17 ns
Switching Characteristics:
tSD CLKOUT High to xMS, RD, WR Disable 0.25 tCK + 10 ns
tSDB xMS, RD, WR Disable to BG Low 0 ns
tSE BG High to xMS, RD, WR Enable 0 ns
tSEC xMS, RD, WR Enable to CLKOUT High 0.25 tCK  7 ns
tSDBH xMS, RD, WR Disable to BGH Low2 0ns
tSEH BGH High to xMS, RD, WR Enable2 0ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User s Manual, Third Edition, for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
WR tSD
tSEC
BG
tSDB
tSE
BGH
tSDBH
tSEH
Figure 11.#$ Bus Request Bus Grant
REV. 0
 17
ADSP-2184
TIMING PARAMETERS
Parameter Min Max Unit
Memory Read
Timing Requirements:
tRDD RD Low to Data Valid 0.5 tCK  9 + w ns
tAA A0 A13, xMS to Data Valid 0.75 tCK  12.5 + w ns
tRDH Data Hold from RD High 1 ns
Switching Characteristics:
tRP RD Pulsewidth 0.5 tCK  5 + w ns
tCRD CLKOUT High to RD Low 0.25 tCK  5 0.25 tCK + 7 ns
tASR A0 A13, xMS Setup before RD Low 0.25 tCK  6 ns
tRDA A0 A13, xMS Hold after RD Deasserted 0.25 tCK  3 ns
tRWR RD High to RD or WR Low 0.5 tCK  5 ns
w = wait states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0  A13
DMS, PMS,
BMS, IOMS,
CMS
tRDA
RD
tASR
tRP
tRWR
tCRD
D
tRDD
tRDH
tAA
WR
Figure 12.#$ Memory Read
REV. 0
 18
ADSP-2184
Parameter Min Max Unit
Memory Write
Switching Characteristics:
tDW Data Setup before WR High 0.5 tCK  7+ w ns
tDH Data Hold after WR High 0.25 tCK  2 ns
tWP WR Pulsewidth 0.5 tCK  5 + w ns
tWDE WR Low to Data Enabled 0 ns
tASW A0 A13, xMS Setup before WR Low 0.25 tCK  6 ns
tDDR Data Disable before WR or RD Low 0.25 tCK  7 ns
tCWR CLKOUT High to WR Low 0.25 tCK  5 0.25 tCK + 7 ns
tAW A0 A13, xMS, Setup before WR Deasserted 0.75 tCK  9 + w ns
tWRA A0 A13, xMS Hold after WR Deasserted 0.25 tCK  3 ns
tWWR WR High to RD or WR Low 0.5 tCK  5 ns
w = wait states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0 A13
DMS, PMS,
BMS, CMS,
IOMS
tWRA
WR
tASW tWP tWWR
tAW
tDH tDDR
tCWR
D
tDW
tWDE
RD
Figure 13.#$ Memory Write
REV. 0
 19
ADSP-2184
TIMING PARAMETERS
Parameter Min Max Unit
Serial Ports
Timing Requirements:
tSCK SCLK Period 50 ns
tSCS DR/TFS/RFS Setup before SCLK Low 4 ns
tSCH DR/TFS/RFS Hold after SCLK Low 8 ns
tSCP SCLKIN Width 20 ns
Switching Characteristics:
tCC CLKOUT High to SCLKOUT 0.25 tCK 0.25 tCK + 10 ns
tSCDE SCLK High to DT Enable 0 ns
tSCDV SCLK High to DT Valid 15 ns
tRH TFS/RFSOUT Hold after SCLK High 0 ns
tRD TFS/RFSOUT Delay from SCLK High 15 ns
tSCDH DT Hold after SCLK High 0 ns
tTDE TFS (Alt) to DT Enable 0 ns
tTDV TFS (Alt) to DT Valid 14 ns
tSCDD SCLK High to DT Disable 15 ns
tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid 15 ns
CLKOUT
tCC tCC
tSCK
SCLK
tSCP
tSCS tSCH tSCP
DR
TFSIN
RFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFSOUT
ALTERNATE
FRAME MODE
tRDV
RFSOUT
MULTICHANNEL
MODE,
FRAME DELAY 0
tTDE
(MFD = 0)
tTDV
TFSIN
ALTERNATE
FRAME MODE
tRDV
RFSIN
MULTICHANNEL
MODE,
FRAME DELAY 0
(MFD = 0)
Figure 14. Serial Ports
REV. 0
 20
ADSP-2184
Parameter Min Max Unit
IDMA Address Latch
Timing Requirements:
tIALP Duration of Address Latch1, 2 10 ns
tIASU IAD15 0 Address Setup before Address Latch End2 5ns
tIAH IAD15 0 Address Hold after Address Latch End2 3ns
tIKA IACK Low before Start of Address Latch2, 3 0ns
tIALS Start of Write or Read after Address Latch End2, 3 3ns
NOTES
1
Start of Address Latch = IS Low and IAL High.
2
End of Address Latch = IS High or IAL Low.
3
Start of Write or Read = IS Low and IWR Low or IRD Low.
IACK
tIKA
IAL
tIALP
IS
tIASU tIAH
IAD 15 0
tIALS
IRD OR
IWR
Figure 15. IDMA Address Latch
REV. 0
 21
ADSP-2184
TIMING PARAMETERS
Parameter Min Max Unit
IDMA Write, Short Write Cycle
Timing Requirements:
tIKW IACK Low before Start of Write1 0ns
tIWP Duration of Write1, 2 15 ns
tIDSU IAD15 0 Data Setup before End of Write2, 3, 4 5ns
tIDH IAD15 0 Data Hold after End of Write2, 3, 4 2ns
Switching Characteristic:
tIKHW Start of Write to IACK High 15 ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
End of Write = IS High or IWR High.
3
If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH.
4
If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.
tIKW
IACK
tIKHW
IS
tIWP
IWR
tIDH
tIDSU
IAD 15 0 DATA
Figure 16. IDMA Write, Short Write Cycle
REV. 0
 22
ADSP-2184
Parameter Min Max Unit
IDMA Write, Long Write Cycle
Timing Requirements:
tIKW IACK Low before Start of Write1 0ns
tIKSU IAD15 0 Data Setup before IACK Low2, 3, 4 0.5 tCK + 10 ns
tIKH IAD15 0 Data Hold after IACK Low2, 3, 4 2ns
Switching Characteristics:
tIKLW Start of Write to IACK Low4 1.5 tCK ns
tIKHW Start of Write to IACK High 15 ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH.
3
If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.
4
This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User s Manual, Third Edition.
tIKW
IACK
tIKHW
tIKLW
IS
IWR
tIKSU
tIKH
IAD 15 0 DATA
Figure 17. IDMA Write, Long Write Cycle
REV. 0
 23
ADSP-2184
TIMING PARAMETERS
Parameter Min Max Unit
IDMA Read, Long Read Cycle
Timing Requirements:
tIKR IACK Low before Start of Read1 0ns
tIRK End of Read after IACK Low 2 ns
Switching Characteristics:
tIKHR IACK High after Start of Read1 15 ns
tIKDS IAD15 0 Data Setup before IACK Low 0.5 tCK  10 ns
tIKDH IAD15 0 Data Hold after End of Read2 0ns
tIKDD IAD15 0 Data Disabled after End of Read2 10 ns
tIRDE IAD15 0 Previous Data Enabled after Start of Read 0 ns
tIRDV IAD15 0 Previous Data Valid after Start of Read 15 ns
tIRDH1 IAD15 0 Previous Data Hold after Start of Read (DM/PM1)3 2 tCK  5 ns
tIRDH2 IAD15 0 Previous Data Hold after Start of Read (PM2)4 tCK  5 ns
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
3
DM read or first half of PM read.
4
Second half of PM read.
IACK
tIKHR
tIKR
IS
tIRK
IRD
tIKDH
tIKDS
tIRDE
PREVIOUS READ
IAD 15 0
DATA DATA
tIRDV tIKDD
tIRDH
Figure 18. IDMA Read, Long Read Cycle
REV. 0
 24
ADSP-2184
Parameter Min Max Unit
IDMA Read, Short Read Cycle
Timing Requirements:
tIKR IACK Low before Start of Read1 0ns
tIRP Duration of Read 15 ns
Switching Characteristics:
tIKHR IACK High after Start of Read1 15 ns
tIKDH IAD15 0 Data Hold after End of Read2 0ns
tIKDD IAD15 0 Data Disabled after End of Read2 10 ns
tIRDE IAD15 0 Previous Data Enabled after Start of Read 0 ns
tIRDV IAD15 0 Previous Data Valid after Start of Read 15 ns
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
IACK
tIKR
tIKHR
IS
tIRP
IRD
tIKDH
tIRDE
PREVIOUS
IAD 15 0
DATA
tIKDD
tIRDV
Figure 19.#$ IDMA Read, Short Read Cycle
REV. 0
 25
ADSP-2184
OUTPUT DRIVE CURRENTS
2184 POWER, INTERNAL1, 2, 3
400
Figure 20 shows typical I-V characteristics for the output drivers
385mW
VDD = 5.5V
375
of the ADSP-2184. The curves represent the current drive
350
capability of the output drivers as a function of output voltage.
325
330mW
60
300mW
300
VDD = 5.0V
VDD = 5.0V @ +25 C
275
VOH
40
250
250mW
VDD = 5.5V @  40 C
225 VDD = 4.5V 225mW
20
200
VDD = 4.5V @ +85 C
180mW
175
150
0
33.33 40
1/tCYC  MHz
VDD = 4.5V @ +85 C
 20
VDD = 5.0V @ +25 C
POWER, IDLE1, 2, 4
VOL 95
91.52mW
90 VDD = 5.5V
 40
85
82.28mW
80
VDD = 5.5V @  40 C
 60
0
10 20 30 40 50 60 75
SOURCE VOLTAGE  V 70.55mW
70 VDD = 5.0V
65
Figure 20. Typical Drive Currents
62.1mW
60
55
POWER DISSIPATION
51.705mW
VDD = 4.5V
50
To determine total power dissipation in a specific application,
45
44.73mW
the following equation should be applied for each output:
40
33.33 40
C × VDD2 × f
1/tCYC  MHz
C = load capacitance, f = output switching frequency.
POWER, IDLE n MODES2
75
Example
IDLE
70.55mW
70
In an application where external data memory is used and no
65
other outputs are active, power dissipation is calculated as follows:
62.1mW
60
Assumptions
55
" External data memory is accessed every cycle with 50% of the
50
address pins switching.
45
40
" External data memory writes occur every other cycle with
36.6mW
34.7mW
IDLE (16)
35
50% of the data pins switching.
IDLE (128)
34.3mW
32.8mW
30
" Each address and data pin has a 10 pF total load at the pin.
25
33.33
40
" The application operates at VDD = 5.0 V and tCK = 25 ns.
1/tCYC  MHz
Total Power Dissipation = PINT + (C × VDD2 × f) VALID FOR ALL TEMPERATURE GRADES.
1
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
PINT = internal power dissipation from Power vs. Frequency
2
IDD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL
graph (Figure 21).
MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14)
30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.
(C × VDD2 × f) is calculated for each output:
3
IDLE REFERS TO ADSP-2184 STATE OF OPERATION DURING EXECUTION OF IDLE
INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
# of
4
TYPICAL POWER DISSIPATION AT 5.0V VDD AND TA = 25 C EXCEPT WHERE SPECIFIED.
Pins C VDD2 f
Figure 21. Power vs. Frequency
Address, DMS 8 × 10 pF × 52 V × 40 MHz = 80 mW
Data Output, WR 9 × 10 pF × 52 V × 20 MHz = 45 mW
RD 1 × 10 pF × 52 V × 20 MHz = 5 mW
CLKOUT 1 × 10 pF × 52 V × 40 MHz = 10 mW
140 mW
Total power dissipation for this example is PINT + 40 mW.
REV. 0
 26
INT
POWER (P
)  mW
SOURCE CURRENT  mA
IDLE
POWER (P
)  mW
IDLE
POWER (P
)  mW
ADSP-2184
CAPACITIVE LOADING is calculated. If multiple pins (such as the data bus) are dis-
Figures 22 and 23 show the capacitive loading characteristics of abled, the measurement value is that of the last pin to stop
the ADSP-2184. driving.
30
T = +85 C INPUT
1.5V 1.5V
OR
VDD = 4.5V
OUTPUT
25
Figure 24. Voltage Reference Levels for AC Measure-
20
ments (Except Output Enable/Disable)
Output Enable Time
15
Output pins are considered to be enabled when that have made
a transition from a high-impedance state to when they start
10
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
5
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
0
the data bus) are enabled, the measurement value is that of the
0 50 100 150 200 250 300
CL  pF first pin to start driving.
Figure 22. Typical Output Rise Time vs. Load Capacitance,
REFERENCE
CL (at Maximum Ambient Operating Temperature)
SIGNAL
tMEASURED
18
tENA
tDIS
VOH VOH
16
(MEASURED) (MEASURED)
14
VOH (MEASURED)  0.5V
2.0V
12
OUTPUT
1.0V
VOL (MEASURED) +0.5V
10
VOL VOL
tDECAY
8 (MEASURED) (MEASURED)
6 OUTPUT
STARTS
OUTPUT STOPS
4
DRIVING DRIVING
2
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
NOMINAL
 2
Figure 25. Output Enable/Disable
 4
 6 IOL
0 50 100 150 200 250
CL  pF
Figure 23. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
TO
Temperature)
OUTPUT +1.5V
PIN
50pF
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
IOH
output high or low voltage to a high impedance state. The out-
Figure 26. Equivalent Device Loading for AC Measure-
put disable time (tDIS) is the difference of tMEASURED and tDECAY,
ments (Including All Fixtures)
as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage. The decay time,
tDECAY, is dependent on the capacitive load, CL, and the current
load, iL, on the output pin. It can be approximated by the fol-
lowing equation:
CL × 0.5V
tDECAY =
iL
from which
tDIS = tMEASURED  tDECAY
REV. 0
 27
RISE TIME (0.4V 2.4V)  ns
VALID OUTPUT DELAY OR HOLD  ns
ADSP-2184
ENVIRONMENTAL CONDITIONS
10k
Ambient Temperature Rating:
TAMB = TCASE  (PD ¸ )
CA
5.6V
TCASE = Case Temperature in °C
1k
PD = Power Dissipation in W
¸ = Thermal Resistance (Case-to-Ambient)
CA
5.0V
¸ = Thermal Resistance (Junction-to-Ambient)
JA
100
¸ = Thermal Resistance (Junction-to-Case)
JC
Package JA
10
JC CA
LQFP 50° C/W 2° C/W 48° C/W
1
20 40 60 80 100 120
0
TEMPERATURE  C
Figure 27. Power-Down Supply Current
REV. 0
 28
IDD 
A
ADSP-2184
100-Lead LQFP Package Pinout
75
A4/IAD3 1 D15
PIN 1
A5/IAD4 2 74 D14
IDENTIFIER
GND 3 73 D13
A6/IAD5 4 72
D12
A7/IAD6 5 71
GND
A8/IAD7 6 70
D11
A9/IAD8 7 69 D10
A10/IAD9 8 68
D9
9 67
A11/IAD10 VDD
10 66
A12/IAD11 GND
11 65
A13/IAD12 D8
12
GND 64 D7/IWR
ADSP-2184
13 63
CLKIN D6/IRD
TOP VIEW
14 62 D5/IAL
XTAL
(Not to Scale)
VDD 15 61
D4/IS
16 60
CLKOUT GND
GND 17 59 VDD
D3/IACK
18 58
VDD
19 57 D2/IAD15
WR
RD 20 56 D1/IAD14
21 55
BMS D0/IAD13
DMS 22 54
BG
PMS 23 53
EBG
24 52
IOMS
BR
25 51
CMS EBR
REV. 0
 29
A0
PWD
A2/IAD1
FL2
PF0 [MODE A]
FL0
D17
D16
D21
D20
D18
D22
D19
D23
GND
PF2 [MODE C]
91
88
PF3
86
FL1
83
81
78
95
BGH
94
92 GND
90 VDD
89
87
85
84
82
80
79
77
76
98
A1/IAD0
96
PWDACK
93
PF1 [MODE B]
99
97
100 A3/IAD2
40
50
48
28
33
35
41
42
47
31
26
34
EE
46
DT1
37
DT0
DR1
DR0
VDD
36
EMS
45
EINT
GND
GND
ELIN
49
TFS1
38
TFS0
32
RFS0
RFS1
39
ECLK
SCLK0
SCLK1
ELOUT
RESET
44
ERESET
43
IRQ2
+PF7
30
IRQE
+PF4
IRQL0
+PF5
27
IRQL1
+PF6
29
ADSP-2184
The ADSP-2184 package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when
Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in
brackets [#$ ] are state bits latched from the value of the pin at the deassertion of RESET.
LQFP Pin Configurations
LQFP Pin LQFP Pin LQFP Pin LQFP Pin
Number Name Number Name Number Name Number Name
1 A4/IAD3 26 IRQE + PF4 51 EBR 76 D16
2 A5/IAD4 27 IRQL0 + PF5 52 BR 77 D17
3GND 28 GND53 EBG 78 D18
4 A6/IAD5 29 IRQL1 + PF6 54 BG 79 D19
5 A7/IAD6 30 IRQ2 + PF7 55 D0/IAD13 80 GND
6 A8/IAD7 31 DT0 56 D1/IAD14 81 D20
7 A9/IAD8 32 TFS0 57 D2/IAD15 82 D21
8 A10/IAD9 33 RFS0 58 D3/IACK 83 D22
9 A11/IAD10 34 DR0 59 VDD 84 D23
10 A12/IAD11 35 SCLK0 60 GND 85 FL2
11 A13/IAD12 36 VDD 61 D4/IS 86 FL1
12 GND 37 DT1 62 D5/IAL 87 FL0
13 CLKIN 38 TFS1 63 D6/IRD 88 PF3
14 XTAL 39 RFS1 64 D7/IWR 89 PF2 [Mode C]
15 VDD 40 DR1 65 D8 90 VDD
16 CLKOUT 41 GND 66 GND 91 PWD
17 GND 42 SCLK1 67 VDD 92 GND
18 VDD 43 ERESET 68 D9 93 PF1 [Mode B]
19 WR 44 RESET 69 D10 94 PF0 [Mode A]
20 RD 45 EMS 70 D11 95 BGH
21 BMS 46 EE 71 GND 96 PWDACK
22 DMS 47 ECLK 72 D12 97 A0
23 PMS 48 ELOUT 73 D13 98 A1/IAD0
24 IOMS 49 ELIN 74 D14 99 A2/IAD1
25 CMS 50 EINT 75 D15 100 A3/IAD2
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ADSP-2184
ORDERING GUIDE
Ambient Instruction
Temperature Rate Package Package
Part Number Range (MHz) Description Option*
ADSP-2184BST-160  40° C to +85° C 40.0 100-Lead LQFP ST-100
*ST = Plastic Thin Quad Flatpack (LQFP).
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
100-Lead Metric Thin Plastic Quad Flatpack (LQFP)
(ST-100)
0.640 (16.25)
0.630 (16.00) TYP SQ
0.620 (15.75)
0.553 (14.05)
0.551 (14.00) TYP SQ
0.549 (13.95)
0.063 (1.60) MAX
0.472 (12.00) BSC
0.030 (0.75)
0.024 (0.60) TYP
100 76
0.020 (0.50) 12
1 75
TYP
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.004
(0.102)
25 51
MAX LEAD
26 50
COPLANARITY 6 Ä… 4
0  7
0.007 (0.177) 0.020 (0.50)
0.011 (0.27)
BSC
0.005 (0.127) TYP
0.009 (0.22) TYP
0.003 (0.077)
LEAD PITCH
0.007 (0.17)
LEAD WIDTH
NOTE:
THE ACTUAL POSITION OF EACH LEAD IS WITHIN (0.08) 0.0032 FROM
ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION.
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED
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C3418 2 5/99
PRINTED IN U.S.A.