a
DSP Microcomputer
ADSP-2183
FUNCTIONAL BLOCK DIAGRAM
FEATURES
PERFORMANCE
POWERDOWN PROGRAMMABLE
19 ns Instruction Cycle Time from 26.32 MHz Crystal CONTROL I/O
@ 3.3 Volts
FLAGS
MEMORY
DATA ADDRESS
PROGRAM
52 MIPS Sustained Performance GENERATORS
PROGRAM DATA
SEQUENCER BYTE DMA
MEMORY MEMORY
DAG 1 DAG 2
Single-Cycle Instruction Execution CONTROLLER
EXTERNAL
Single-Cycle Context Switch
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
3-Bus Architecture Allows Dual Operand Fetches in
DATA MEMORY ADDRESS
Every Instruction Cycle
Multifunction Instructions PROGRAM MEMORY DATA
Power-Down Mode Featuring Low CMOS Standby DATA MEMORY DATA
EXTERNAL
Power Dissipation with 300 Cycle Recovery from DATA
BUS
Power-Down Condition
ARITHMETIC UNITS SERIAL PORTS
TIMER INTERNAL
DMA
Low Power Dissipation in Idle Mode
ALU MAC SHIFTER SPORT 0 SPORT 1
PORT
DMA
BUS
INTEGRATION
ADSP-2100 BASE
ARCHITECTURE
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
80K Bytes of On-Chip RAM, Configured as
GENERAL DESCRIPTION
16K Words On-Chip Program Memory RAM
The ADSP-2183 is a single-chip microcomputer optimized for
16K Words On-Chip Data Memory RAM
digital signal processing (DSP) and other high speed numeric
Dual Purpose Program Memory for Both Instruction
processing applications.
and Data Storage
The ADSP-2183 combines the ADSP-2100 family base architec-
Independent ALU, Multiplier/Accumulator, and Barrel
ture (three computational units, data address generators and
Shifter Computational Units
a program sequencer) with two serial ports, a 16-bit internal
Two Independent Data Address Generators
Powerful Program Sequencer Provides DMA port, a byte DMA port, a programmable timer, Flag I/O,
Zero Overhead Looping extensive interrupt capabilities, and on-chip program and
Conditional Instruction Execution
data memory.
Programmable 16-Bit Interval Timer with Prescaler
The ADSP-2183 integrates 80K bytes of on-chip memory con-
128-Lead LQFP, 144-Ball Mini-BGA
figured as 16K words (24-bit) of program RAM, and 16K words
SYSTEM INTERFACE
(16-bit) of data RAM. Power-down circuitry is also provided to
16-Bit Internal DMA Port for High Speed Access to
meet the low power needs of battery operated portable equipment.
On-Chip Memory
The ADSP-2183 is available in 128-lead LQFP, and 144-Ball
4 MByte Memory Interface for Storage of Data Tables
Mini-BGA packages.
and Program Overlays
In addition, the ADSP-2183 supports new instructions, which
8-Bit DMA to Byte Memory for Transparent
include bit manipulations bit set, bit clear, bit toggle, bit test
Program and Data Memory Transfers
new ALU constants, new multiplication instruction (x squared),
I/O Memory Interface with 2048 Locations Supports
biased rounding, result free ALU operations, I/O memory trans-
Parallel Peripherals
Programmable Memory Strobe and Separate I/O fers and global interrupt masking, for increased flexibility.
Memory Space Permits  Glueless System Design
Fabricated in a high speed, double metal, low power, CMOS
Programmable Wait State Generation
process, the ADSP-2183 operates with a 19 ns instruction cycle
Two Double-Buffered Serial Ports with Companding
time. Every instruction can execute in a single processor cycle.
Hardware and Automatic Data Buffering
The ADSP-2183 s flexible architecture and comprehensive
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or instruction set allow the processor to perform multiple opera-
Through Internal DMA Port tions in parallel. In one processor cycle the ADSP-2183 can:
Six External Interrupts
" Generate the next program address
13 Programmable Flag Pins Provide Flexible System
" Fetch the next instruction
Signaling
" Perform one or two data moves
ICE-Port"! Emulator Interface Supports Debugging
" Update one or two data address pointers
in Final Systems
" Perform a computational operation
ICE-Port is a trademark of Analog Devices, Inc.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
use, nor for any infringements of patents or other rights of third parties
Tel: [phone] World Wide Web Site: http://www.analog.com
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices. Fax: [phone] © Analog Devices, Inc., 2000
ADSP-2183
This takes place while the processor continues to: ARCHITECTURE OVERVIEW
" Receive and transmit data through the two serial ports The ADSP-2183 instruction set provides flexible data moves
" Receive and/or transmit data through the internal DMA port and multifunction (one or two data moves with a computation)
" Receive and/or transmit data through the byte DMA port instructions. Every instruction can be executed in a single pro-
" Decrement timer cessor cycle. The ADSP-2183 assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
Development System
set of development tools supports program development.
The ADSP-2100 Family Development Software, a complete
Figure 1 is an overall block diagram of the ADSP-2183. The
set of tools for software and hardware system development,
processor contains three independent computational units: the
supports the ADSP-2183. The assembler has an algebraic syntax
ALU, the multiplier/accumulator (MAC) and the shifter. The
that is easy to program and debug. The linker combines object
computational units process 16-bit data directly and have provi-
files into an executable file. The simulator provides an interactive
sions to support multiprecision computations. The ALU per-
instruction-level simulation with a reconfigurable user interface
forms a standard set of arithmetic and logic operations; division
to display different portions of the hardware environment.
primitives are also supported. The MAC performs single-cycle
The EZ-KIT Lite is a hardware/software kit offering a com-
multiply, multiply/add and multiply/subtract operations with
plete development environment for the ADSP-21xx family:
40 bits of accumulation. The shifter performs logical and arith-
an ADSP-2189M evaluation board with PC monitor software
metic shifts, normalization, denormalization and derive
plus Assembler, Linker, Simulator and PROM Splitter software.
exponent operations. The shifter can be used to efficiently
The ADSP-2189M evaluation board is a low-cost, easy to use
implement numeric format control including multiword and
hardware platform on which you can quickly get started with
block floating-point representations.
your DSP software design. The EZ-KIT Lite include the
The internal result (R) bus connects the computational units so
following features:
that the output of any unit may be the input of any unit on the
" 35.7 MHz ADSP-2189M
next cycle.
" Full 16-bit Stereo Audio I/O with AD73322 CODEC
The ADSP-21xx family DSPs contain a shadow register that is
" RS-232 Interface
useful for single cycle context switching of the processor.
" EZ-ICE Connector for Emulator Control
" DSP Demo Programs
A powerful program sequencer and two dedicated data address
" Evaluation Suite of VisualDSP
generators ensure efficient delivery of operands to these compu-
The ADSP-218x EZ-ICE® Emulator aids in the hardware debug- tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
ging of ADSP-218x systems. The ADSP-218x integrates on-chip
emulation support with a 14-pin ICE-Port interface. This inter- counters and loop stacks, the ADSP-2183 executes looped code
with zero overhead; no explicit jump instructions are required to
face provides a simpler target board connection requiring fewer
maintain loops.
mechanical clearance considerations than other ADSP-2100
Family EZ-ICEs. The ADSP-218x device need not be removed
Two data address generators (DAGs) provide addresses for
from the target system when using the EZ-ICE, nor are any
simultaneous dual operand fetches (from data memory and
adapters needed. Due to the small footprint of the EZ-ICE
program memory). Each DAG maintains and updates four
connector, emulation can be supported in final board designs.
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
The EZ-ICE performs a full range of functions, including:
four possible modify registers. A length value may be associated
" In-target operation
with each pointer to implement automatic modulo addressing
" Up to 20 breakpoints
for circular buffers.
" Single-step or full-speed operation
Efficient data transfer is achieved with the use of five internal
" Registers and memory values can be examined and altered
buses:
" PC upload and download functions
" Instruction-level emulation of program booting and execution
" Program Memory Address (PMA) Bus
" Complete assembly and disassembly of instructions
" Program Memory Data (PMD) Bus
" C source-level debugging
" Data Memory Address (DMA) Bus
" Data Memory Data (DMD) Bus
(See Designing An EZ-ICE-Compatible Target System section
" Result (R) Bus
of this data sheet for exact specifications of the EZ-ICE target
The two address buses (PMA and DMA) share a single external
board connector.)
address bus, allowing memory to be expanded off-chip, and the
Additional Information
two data buses (PMD and DMD) share a single external data
This data sheet provides a general overview of ADSP-2183
bus. Byte memory space and I/O memory space also share the
functionality. For additional information on the architecture and
external buses.
instruction set of the processor, refer to the ADSP-2100 Family
Program memory can store both instructions and data, permit-
User s Manual, Third Edition. For more information about the
ting the ADSP-2183 to fetch two operands in a single cycle,
development tools, refer to the ADSP-2100 Family Development
one from program memory and one from data memory. The
Tools Data Sheet.
ADSP-2183 can fetch an operand from program memory and
the next instruction in the same cycle.
EZ-ICE and SoundPort are registered trademarks of Analog Devices, Inc.
 2 REV. C
ADSP-2183
In addition to the address and data bus for external memory The ADSP-2183 provides up to 13 general-purpose flag pins.
connection, the ADSP-2183 has a 16-bit Internal DMA port The data input and output pins on SPORT1 can be alternatively
(IDMA port) for connection to external systems. The IDMA configured as an input flag and an output flag. In addition, eight
port is made up of 16 data/address pins and five control pins. flags are programmable as inputs or outputs and three flags are
The IDMA port provides transparent, direct access to the DSPs always outputs.
on-chip program and data RAM.
A programmable interval timer generates periodic interrupts. A
An interface to low cost byte-wide memory is provided by the
16-bit count register (TCOUNT) is decremented every n pro-
Byte DMA port (BDMA port). The BDMA port is bidirectional
cessor cycle, where n is a scaling value stored in an 8-bit register
and can directly address up to four megabytes of external RAM
(TSCALE). When the value of the count register reaches zero,
or ROM for off-chip storage of program overlays or data tables.
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with pro-
Serial Ports
grammable wait state generation. External devices can gain
The ADSP-2183 incorporates two complete synchronous serial
control of external buses with bus request/grant signals (BR,
ports (SPORT0 and SPORT1) for serial communications and
BGH and BG). One execution mode (Go Mode) allows the
multiprocessor communication.
ADSP-2183 to continue running from on-chip memory. Normal
Here is a brief list of the capabilities of the ADSP-2183
execution mode requires the processor to halt while buses are
SPORTs. Refer to the ADSP-2100 Family User s Manual, Third
granted.
Edition, for further details.
The ADSP-2183 can respond to thirteen possible interrupts,
" SPORTs are bidirectional and have a separate, double-
eleven of which are accessible at any given time. There can be
buffered transmit and receive section.
up to six external interrupts (one edge-sensitive, two level-
sensitive and three configurable) and seven internal interrupts " SPORTs can use an external serial clock or generate their
generated by the timer, the serial ports (SPORTs), the Byte own serial clock internally.
DMA port and the power-down circuitry. There is also a master
" SPORTs have independent framing for the receive and trans-
RESET signal.
mit sections. Sections run in a frameless mode or with frame
The two serial ports provide a complete synchronous serial inter- synchronization signals, internally or externally generated.
face with optional companding in hardware and a wide variety of Frame sync signals are active high or inverted, with either of
framed or frameless data transmit and receive modes of operation. two pulsewidths and timings.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
21xx CORE ADSP-2183 INTEGRATION
2
POWER
DOWN
CONTROL
LOGIC
INSTRUCTION PROGRAM DATA
REGISTER SRAM
SRAM
8
16k 24
PROGRAMMABLE
16k 16 BYTE
DMA I/O
CONTROLLER
DATA DATA 3
ADDRESS ADDRESS
PROGRAM
FLAGS
GENERATOR GENERATOR
SEQUENCER
#1 #2
PMA BUS 14 PMA BUS
14
MUX
DMA BUS 14 DMA BUS
EXTERNAL
ADDRESS
BUS
PMD BUS 24 PMD BUS
EXTERNAL
DATA
BUS
BUS
MUX
EXCHANGE
DMD
DMD BUS
BUS
24
16
INPUT REGS INPUT REGS
INPUT REGS INPUT REGS INPUT REGS
COMPANDING 16
INTERNAL
CIRCUITRY
DMA
PORT
ALU MAC
ALU MAC SHIFTER
TIMER
TRANSMIT REG TRANSMIT REG
OUTPUT REGS OUTPUT REGS
OUTPUT REGS OUTPUT REGS OUTPUT REGS
RECEIVE REG RECEIVE REG
4
SERIAL
16 SERIAL
PORT 0 PORT 0 INTERRUPTS
R BUS
5 5
Figure 1. Block Diagram
REV. C
 3
ADSP-2183
" SPORTs support serial data word lengths from 3 to 16 bits
#
and provide optional A-law and µ-law companding according
Pin of Input/
to CCITT recommendation G.711.
Name(s) Pins Output Function
" SPORT receive and transmit sections can generate unique
CLKOUT 1 O Processor Clock Output.
interrupts on completing a data word transfer.
SPORT0 5 I/O Serial Port I/O Pins
" SPORTs can receive and transmit an entire circular buffer of
SPORT1 5 I/O Serial Port 1 or Two External
data with only one overhead cycle per data word. An interrupt
IRQs, Flag In and Flag Out
is generated after a data buffer transfer.
IRD, IWR 2 I IDMA Port Read/Write Inputs
" SPORT0 has a multichannel interface to selectively receive
IS 1 I IDMA Port Select
and transmit a 24 or 32 word, time-division multiplexed,
IAL 1 I IDMA Port Address Latch
serial bitstream.
Enable
" SPORT1 can be configured to have two external interrupts
IAD 16 I/O IDMA Port Address/Data Bus
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
IACK 1 O IDMA Port Access Ready
internally generated serial clock may still be used in this
Acknowledge
configuration.
PWD 1 I Power-Down Control
Pin Descriptions
PWDACK 1 O Power-Down Control
The ADSP-2183 is available in a 128-lead LQFP package, and
Mini-BGA. FL0, FL1,
FL2 3 O Output Flags
PIN FUNCTION DESCRIPTIONS
PF7:0 8 I/O Programmable I/O Pins
#
EE 1 * (Emulator Only*)
Pin of Input/
EBR 1 * (Emulator Only*)
Name(s) Pins Output Function
EBG 1 * (Emulator Only*)
Address 14 O Address Output Pins for Program,
ERESET 1 * (Emulator Only*)
Data, Byte, & I/O Spaces
EMS 1 * (Emulator Only*)
Data 24 I/O Data I/O Pins for Program and
EINT 1 * (Emulator Only*)
Data Memory Spaces (8 MSBs
ECLK 1 * (Emulator Only*)
Are Also Used as Byte Space
Addresses) ELIN 1 * (Emulator Only*)
RESET 1 I Processor Reset Input ELOUT 1 * (Emulator Only*)
IRQ2 1 I Edge- or Level-Sensitive GND 11 Ground Pins (LQFP)
Interrupt Request
VDD 6 Power Supply Pins (LQFP)
IRQL0,
GND 22 Ground Pins (Mini-BGA)
IRQL1 2 I Level-Sensitive Interrupt
VDD 11 Power Supply Pins (Mini-BGA)
Requests
*These ADSP-2183 pins must be connected only to the EZ-ICE connector in
IRQE 1 I Edge-Sensitive Interrupt
the target system. These pins have no function except during emulation, and
Request
do not require pull-up or pull-down resistors.
BR 1 I Bus Request Input
Interrupts
BG 1 O Bus Grant Output
The interrupt controller allows the processor to respond to the
BGH 1 O Bus Grant Hung Output
eleven possible interrupts and reset with minimum overhead.
The ADSP-2183 provides four dedicated external interrupt
PMS 1 O Program Memory Select Output
input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition,
DMS 1 O Data Memory Select Output
SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and
BMS 1 O Byte Memory Select Output
FLAG_OUT, for a total of six external interrupts. The ADSP-
IOMS 1 O I/O Space Memory Select Output
2183 also supports internal interrupts from the timer, the byte
CMS 1 O Combined Memory Select Output
DMA port, the two serial ports, software and the power-down
RD 1 O Memory Read Enable Output control circuit. The interrupt levels are internally prioritized and
individually maskable (except power-down and reset). The
WR 1 O Memory Write Enable Output
IRQ2, IRQ0 and IRQ1 input pins can be programmed to be
MMAP 1 I Memory Map Select Input
either level- or edge-sensitive. IRQL0 and IRQL1 are level-
BMODE 1 I Boot Option Control Input
sensitive and IRQE is edge sensitive. The priorities and vector
CLKIN,
addresses of all interrupts are shown in Table I.
XTAL 2 I Clock or Quartz Crystal Input
 4 REV. C
ADSP-2183
Table I. Interrupt Priority and Interrupt Vector Addresses
Power-Down
The ADSP-2183 processor has a low power feature that lets
Interrupt Vector
the processor enter a very low power dormant state through
Source of Interrupt Address (Hex)
hardware or software control. Here is a brief list of power-
down features. Refer to the ADSP-2100 Family User s Manual,
Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Third Edition,  System Interface chapter for detailed
Power-Down (Nonmaskable) 002C
information about the power-down feature.
IRQ2 0004
IRQL1 0008
" Quick recovery from power-down. The processor begins
IRQL0 000C
executing instructions in as few as 300 CLKIN cycles.
SPORT0 Transmit 0010
" Support for an externally generated TTL or CMOS
SPORT0 Receive 0014
processor clock. The external clock can continue running
IRQE 0018
during power-down without affecting the lowest power
BDMA Interrupt 001C
rating and 300 CLKIN cycle recovery.
SPORT1 Transmit or IRQ1 0020
" Support for crystal operation includes disabling the oscil-
SPORT1 Receive or IRQ0 0024
lator to save power (the processor automatically waits 4096
Timer 0028 (Lowest Priority)
CLKIN cycles for the crystal oscillator to start and stabi-
lize), and letting the oscillator run to allow 300 CLKIN
Interrupt routines can either be nested, with higher priority
cycle start-up.
interrupts taking precedence, or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
" Power-down is initiated by either the power-down pin
Individual interrupt requests are logically ANDed with the bits
(PWD) or the software power-down force bit.
in IMASK; the highest priority unmasked interrupt is then
" Interrupt support allows an unlimited number of instruc-
selected. The power-down interrupt is nonmaskable.
tions to be executed before optionally powering down.
The ADSP-2183 masks all interrupts for one instruction cycle
The power-down interrupt also can be used as a non-
following the execution of an instruction that modifies the
maskable, edge-sensitive interrupt.
IMASK register. This does not affect serial port autobuffering
" Context clear/save control allows the processor to con-
or DMA transfers.
tinue where it left off or start with a clean context when
The interrupt control register, ICNTL, controls interrupt nest-
leaving the power-down state.
ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
" The RESET pin also can be used to terminate
be either edge- or level-sensitive. The IRQE pin is an external
power-down.
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts. " Power-down acknowledge pin indicates when the
processor has entered power-down.
The IFC register is a write-only register used to force and clear
interrupts. Idle
When the ADSP-2183 is in the Idle Mode, the processor
On-chip stacks preserve the processor status and are automati-
waits indefinitely in a low power state until an interrupt
cally maintained during interrupt handling. The stacks are
occurs. When an unmasked interrupt occurs, it is serviced;
twelve levels deep to allow interrupt, loop and subroutine nesting.
execution then continues with the instruction following the
The following instructions allow global enable or disable servic-
IDLE instruction.
ing of the interrupts (including power down), regardless of the
Slow Idle
state of IMASK. Disabling the interrupts does not affect serial
The IDLE instruction is enhanced on the ADSP-2183 to
port autobuffering or DMA.
let the processor s internal clock signal be slowed, further
ENA INTS;
reducing power consumption. The reduced clock frequency,
DIS INTS;
a programmable fraction of the normal clock rate, is speci-
fied by a selectable divisor given in the IDLE instruction.
When the processor is reset, interrupt servicing is enabled.
The format of the instruction is
LOW POWER OPERATION
IDLE (n);
The ADSP-2183 has three low power modes that significantly
where n = 16, 32, 64 or 128. This instruction keeps the
reduce the power dissipation when the device operates under
processor fully functional, but operating at the slower clock
standby conditions. These modes are:
rate. While it is in this state, the processor s other internal
" Power-Down
clock signals, such as SCLK, CLKOUT and timer clock,
" Idle
are reduced by the same ratio. The default form of the
" Slow Idle
instruction, when no clock divisor is given, is the standard
IDLE instruction.
The CLKOUT pin may also be disabled to reduce external
power dissipation.
REV. C
 5
ADSP-2183
When the IDLE (n) instruction is used, it effectively slows down If an external clock is used, it should be a TTL-compatible
the processor s internal clock, and thus its response time, to signal running at half the instruction rate. The signal is con-
incoming interrupts. The one-cycle response time of the stan- nected to the processor s CLKIN input. When an external clock
dard idle state is increased by n, the clock divisor. When an is used, the XTAL input must be left unconnected.
enabled interrupt is received, the ADSP-2183 will remain in the
The ADSP-2183 uses an input clock with a frequency equal to
idle state for up to a maximum of n processor cycles (n = 16, 32,
half the instruction rate; a 16.67 MHz input clock yields a 30 ns
64 or 128) before resuming normal operation.
processor cycle (which is equivalent to 33 MHz). Normally,
When the IDLE (n) instruction is used in systems with an exter- instructions are executed in a single processor cycle. All device
nally generated serial clock (SCLK), the serial clock rate may be timing is relative to the internal instruction clock rate, which is
faster than the processor s reduced internal clock rate. Under indicated by the CLKOUT signal when enabled.
these conditions, interrupts must not be generated at a faster
Because the ADSP-2183 includes an on-chip oscillator circuit,
rate than can be serviced, due to the additional time the processor
an external crystal may be used. The crystal should be connected
takes to come out of the idle state (a maximum of n processor
across the CLKIN and XTAL pins, with two capacitors connected
cycles).
as shown in Figure 3. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
SYSTEM INTERFACE
parallel-resonant, fundamental frequency, microprocessor-grade
Figure 2 shows a typical basic system configuration with the
crystal should be used.
ADSP-2183, two serial devices, a byte-wide EPROM and
A clock output (CLKOUT) signal is generated by the processor
optional external program and data overlay memories. Program-
at the processor s cycle rate. This can be enabled and disabled
mable wait state generation allows the processor to connect
by the CLKODIS bit in the SPORT0 Autobuffer Control
easily to slow peripheral devices. The ADSP-2183 also provides
Register.
four external interrupts and two serial ports or six external inter-
rupts and one serial port.
ADSP-2183
XTAL
CLKIN CLKOUT
1/2x CLOCK CLKIN
14 A13-0
OR
ADDR13-0 DSP
XTAL
CRYSTAL
D23-16 A0-A21
FL0-2
BYTE
PF0-7
D15-8
24
MEMORY
DATA23-0 DATA
IRQ2
BMS CS
IRQE Figure 3. External Crystal Connections
IRQL0
A10-0
IRQL1
ADDR
Reset
D23-8
RD
I/O
SPORT1
The RESET signal initiates a master reset of the ADSP-2183.
DATA
WR
SPACE
SCLK1
RFS1 OR IRQ0
(PERIPHERALS) The RESET signal must be asserted during the power-up se-
SERIAL
TFS1 OR IRQ1
DEVICE IOMS CS
DT1 OR FO
quence to assure proper initialization. RESET during initial
2048 LOCATIONS
DR1 OR FI
power-up must be held long enough to allow the internal clock
A13-0
SPORT0
ADDR
OVERLAY
SCLK0 to stabilize. If RESET is activated any time after power-up, the
D23-0
RFS0 MEMORY
SERIAL
DATA
TFS0 clock continues to run and does not require stabilization time.
DEVICE
TWO 8K
DT0 PMS
PM SEGMENTS
DR0
DMS
The power-up sequence is defined as the total time required for
CMS
TWO 8K
IDMA PORT
DM SEGMENTS the crystal oscillator circuit to stabilize after a valid VDD is ap-
BR
IRD
IWR BG
SYSTEM plied to the processor, and for the internal phase-locked loop
IS BGH
INTERFACE
IAL
OR (PLL) to lock onto the specific crystal frequency. A minimum of
PWD
IACK
CONTROLLER
16
PWDACK
IAD15-0
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
Figure 2. ADSP-2183 Basic System Configuration
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
Clock Signals
The ADSP-2183 can be clocked by either a crystal or a TTL- mum pulsewidth specification, tRSP.
compatible clock signal.
The RESET input contains some hysteresis; however, if you use
The CLKIN input cannot be halted, changed during operation an RC circuit to generate your RESET signal, the use of an
or operated below the specified frequency during normal opera- external Schmidt trigger is recommended.
tion. The only exception is while the processor is in the power-
The master reset sets all internal stack pointers to the empty
down state. For additional information, refer to Chapter 9,
stack condition, masks all interrupts and clears the MSTAT
ADSP-2100 Family User s Manual, Third Edition, for detailed
register. When RESET is released, if there is no pending bus
information on this power-down feature.
request and the chip is configured for booting (MMAP = 0), the
boot-loading sequence is performed. The first instruction is
fetched from on-chip program memory location 0x0000 once
boot loading completes.
 6 REV. C
ADSP-2183
Table II.
Memory Architecture
The ADSP-2183 provides a variety of memory and peripheral
PMOVLAY Memory A13 A12:0
interface options. The key functional groups are Program
Memory, Data Memory, Byte Memory and I/O.
0 Internal Not Applicable Not Applicable
Program Memory is a 24-bit-wide space for storing both
1 External 0 13 LSBs of Address
instruction opcodes and data. The ADSP-2183 has 16K words
Overlay 1 Between 0x2000
of Program Memory RAM on chip and the capability of access-
and 0x3FFF
ing up to two 8K external memory overlay spaces using the
external data bus. Both an instruction opcode and a data value
2 External 1 13 LSBs of Address
can be read from on-chip program memory in a single cycle.
Overlay 2 Between 0x2000
and 0x3FFF
Data Memory is a 16-bit-wide space used for the storage of
data variables and for memory-mapped control registers. The
This organization provides for two external 8K overlay segments
ADSP-2183 has 16K words on Data Memory RAM on chip,
using only the normal 14 address bits. This allows for simple
consisting of 16,352 user-accessible locations and 32 memory-
program overlays using one of the two external segments in
mapped registers. Support also exists for up to two 8K external
place of the on-chip memory. Care must be taken in using this
memory overlay spaces through the external data bus.
overlay space because the processor core (i.e., the sequencer)
Byte Memory provides access to an 8-bit-wide memory space
does not take the PMOVLAY register value into account. For
through the Byte DMA (BDMA) port. The Byte Memory inter-
example, if a loop operation were occurring on one of the exter-
face provides access to 4 MBytes of memory by utilizing eight
nal overlays, and the program changes to another external over-
data lines as additional address lines. This gives the BDMA Port
lay or internal memory, an incorrect loop operation could occur.
an effective 22-bit address range. On power-up, the DSP can
In addition, care must be taken in interrupt service routines as
automatically load bootstrap code from byte memory.
the overlay registers are not automatically saved and restored on
I/O Space allows access to 2048 locations of 16-bit-wide data.
the processor mode stack.
It is intended to be used to communicate with parallel periph-
For ADSP-2100 Family compatibility, MMAP = 1 is allowed.
eral devices such as data converters and external registers or
In this mode, booting is disabled and overlay memory is dis-
latches.
abled (PMOVLAY must be 0). Figure 5 shows the memory map
Program Memory
in this configuration.
The ADSP-2183 contains a 16K × 24 on-chip program RAM.
PROGRAM MEMORY ADDRESS
The on-chip program memory is designed to allow up to two
0x3FFF
accesses each cycle so that all operations can complete in a
INTERNAL 8K
single cycle. In addition, the ADSP-2183 allows the use of 8K
(PMOVLAY = 0,
external memory overlays.
MMAP = 1)
0x2000
The program memory space organization is controlled by the
0x1FFF
MMAP pin and the PMOVLAY register. Normally, the ADSP-
8K EXTERNAL
2183 is configured with MMAP = 0 and program memory orga-
nized as shown in Figure 4.
0x0000
PROGRAM MEMORY ADDRESS
Figure 5. Program Memory (MMAP = 1)
0x3FFF
8K INTERNAL
Data Memory
(PMOVLAY = 0,
MMAP = 0) The ADSP-2183 has 16,352 16-bit words of internal data
OR
memory. In addition, the ADSP-2183 allows the use of 8K
EXTERNAL 8K
(PMOVLAY = 1 or 2,
external memory overlays. Figure 6 shows the organization of
MMAP = 0)
0x2000
the data memory.
0x1FFF
DATA MEMORY ADDRESS
8K INTERNAL
0x3FFF
32 MEMORY
MAPPED REGISTERS
0x0000
0x3FEO
0x3FDF
Figure 4. Program Memory (MMAP = 0)
INTERNAL
8160 WORDS
There are 16K words of memory accessible internally when the
0x2000
PMOVLAY register is set to 0. When PMOVLAY is set to
0x1FFF
8K INTERNAL
something other than 0, external accesses occur at addresses
(DMOVLAY = 0)
0x2000 through 0x3FFF. The external address is generated as
OR
EXTERNAL 8K
shown in Table II.
(DMOVLAY = 1, 2)
0x0000
Figure 6. Data Memory
REV. C
 7
ADSP-2183
There are 16,352 words of memory accessible internally when The CMS pin functions like the other memory select signals,
the DMOVLAY register is set to 0. When DMOVLAY is set to with the same timing and bus request logic. A 1 in the enable bit
something other than 0, external accesses occur at addresses causes the assertion of the CMS signal at the same time as the
0x0000 through 0x1FFF. The external address is generated as selected memory select signal. All enable bits, except the BMS
shown in Table III. bit, default to 1 at reset.
Byte Memory
Table III.
The byte memory space is a bidirectional, 8-bit-wide, external
DMOVLAY Memory A13 A12:0 memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space
0 Internal Not Applicable Not Applicable
consists of 256 pages, each of which is 16K × 8.
1 External 0 13 LSBs of Address
The byte memory space on the ADSP-2183 supports read and
Overlay 1 Between 0x0000
write operations as well as four different data formats. The byte
and 0x1FFF
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
2 External 1 13 LSBs of Address
This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be
Overlay 2 Between 0x0000
used without glue logic. All byte memory accesses are timed by
and 0x1FFF
the BMWAIT register.
This organization allows for two external 8K overlays using only Byte Memory DMA (BDMA)
the normal 14 address bits. The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
All internal accesses complete in one cycle. Accesses to external
The BDMA circuit is able to access the byte memory space,
memory are timed using the wait states specified by the DWAIT
while the processor is operating normally and steals only one
register.
DSP cycle per 8-, 16- or 24-bit word transferred.
I/O Space
The BDMA circuit supports four different data formats which
The ADSP-2183 supports an additional external memory space
are selected by the BTYPE register field. The appropriate num-
called I/O space. This space is designed to support simple con-
ber of 8-bit accesses are done from the byte memory space to
nections to peripherals or to bus interface ASIC data registers.
build the word size selected. Table V shows the data formats
I/O space supports 2048 locations. The lower eleven bits of the
supported by the BDMA circuit.
external address bus are used; the upper 3 bits are undefined.
Two instructions were added to the core ADSP-2100 Family
Table V.
instruction set to read from and write to I/O memory space.
Internal
The I/O space also has four dedicated 3-bit wait state regis-
BTYPE Memory Space Word Size Alignment
ters, IOWAIT0-3, which specify up to seven wait states to be
automatically generated for each of four regions. The wait states
00 Program Memory 24 Full Word
act on address ranges as shown in Table IV.
01 Data Memory 16 Full Word
10 Data Memory 8 MSBs
Table IV.
11 Data Memory 8 LSBs
Address Range Wait State Register
Unused bits in the 8-bit data memory formats are filled with 0s.
0x000 0x1FF IOWAIT0
The BIAD register field is used to specify the starting address
0x200 0x3FF IOWAIT1
for the on-chip memory involved with the transfer. The 14-bit
0x400 0x5FF IOWAIT2
BEAD register specifies the starting address for the external byte
0x600 0x7FF IOWAIT3
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
Composite Memory Select (CMS)
field selects the direction of the transfer. Finally the 14-bit
The ADSP-2183 has a programmable memory select signal that
BWCOUNT register specifies the number of DSP words to
is useful for generating memory select signals for memories
transfer and initiates the BDMA circuit transfers.
mapped to more than one space. The CMS signal is generated
to have the same timing as each of the individual memory select
BDMA accesses can cross page boundaries during sequential
signals (PMS, DMS, BMS, IOMS) but can combine their
addressing. A BDMA interrupt is generated on the completion
functionality.
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
When set, each bit in the CMSSEL register causes the CMS
be used to check the status of the transfers. When it reaches
signal to be asserted when the selected memory select is as-
zero, the transfers have finished and a BDMA interrupt is gener-
serted. For example, to use a 32K word memory to act as both
ated. The BMPAGE and BEAD registers must not be accessed
program and data memory, set the PMS and DMS bits in the
by the DSP during BDMA operations.
CMSSEL register and use the CMS pin to drive the chip
select of the memory; use either DMS or PMS as the additional
The source or destination of a BDMA transfer will always be
address bit.
on-chip program or data memory, regardless of the values of
MMAP, PMOVLAY or DMOVLAY.
 8 REV. C
ADSP-2183
When the BWCOUNT register is written with a nonzero value Table VI. Boot Summary Table
the BDMA circuit starts executing byte memory accesses with
MMAP BMODE Booting Method
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to create
0 0 BDMA feature is used in default mode
a destination word, it is transferred to or from on-chip memory.
to load the first 32 program memory
The transfer takes one DSP cycle. DSP accesses to external
words from the byte memory space.
memory have priority over BDMA byte memory accesses.
Program execution is held off until all
32 words have been loaded.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
0 1 IDMA feature is used to load any inter-
Setting the BCR bit to 0 allows the processor to continue opera-
nal memory as desired. Program execu-
tions. Setting the BCR bit to 1 causes the processor to stop
tion is held off until internal program
execution while the BDMA accesses are occurring, to clear the
memory location 0 is written to.
context of the processor and start execution at address 0 when
the BDMA accesses have completed.
1 X Bootstrap features disabled. Program
execution immediately starts from
Internal Memory DMA Port (IDMA Port)
location 0.
The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2183. The port is used to
BDMA Booting
access the on-chip program memory and data memory of the
When the BMODE and MMAP pins specify BDMA booting
DSP with only one DSP cycle per word overhead. The IDMA
(MMAP = 0, BMODE = 0), the ADSP-2183 initiates a BDMA
port cannot, however, be used to write to the DSP s memory-
boot sequence when reset is released. The BDMA interface is
mapped control registers.
set up during reset to the following defaults when BDMA boot-
The IDMA port has a 16-bit multiplexed address and data bus
ing is specified: the BDIR, BMPAGE, BIAD and BEAD regis-
and supports 24-bit program memory. The IDMA port is
ters are set to 0, the BTYPE register is set to 0 to specify
completely asynchronous and can be written to while the
program memory 24 bit words, and the BWCOUNT register is
ADSP-2183 is operating at full speed.
set to 32. This causes 32 words of on-chip program memory to
The DSP memory address is latched and then automatically
be loaded from byte memory. These 32 words are used to set up
incremented after each IDMA transaction. An external device
the BDMA to load in the remaining program code. The BCR
can therefore access a block of sequentially addressed memory
bit is also set to 1, which causes program execution to be held
by specifying only the starting address of the block. This in-
off until all 32 words are loaded into on-chip program memory.
creases throughput as the address does not have to be sent for
Execution then begins at address 0.
each memory access.
The ADSP-2100 Family Development Software (Revision 5.02
IDMA Port access occurs in two phases. The first is the IDMA
and later) fully supports the BDMA booting feature and can
Address Latch cycle. When the acknowledge is asserted, a 14-
generate byte memory space compatible boot code.
bit address and 1-bit destination type can be driven onto the bus
The IDLE instruction can also be used to allow the processor to
by an external device. The address specifies an on-chip memory
hold off execution while booting continues through the BDMA
location; the destination type specifies whether it is a DM or
interface.
PM access. The falling edge of the address latch signal latches
IDMA Booting
this value into the IDMAA register.
The ADSP-2183 can also boot programs through its Internal
Once the address is stored, data can either be read from or
DMA port. If BMODE = 1 and MMAP = 0, the ADSP-2183
written to the ADSP-2183 s on-chip memory. Asserting the
boots from the IDMA port. IDMA feature can load as much on-
select line (IS) and the appropriate read or write line (IRD and
chip memory as desired. Program execution is held off until on-
IWR respectively) signals the ADSP-2183 that a particular
chip program memory location 0 is written to.
transaction is required. In either case, there is a one-processor-
The ADSP-2100 Family Development Software (Revision 5.02
cycle delay for synchronization. The memory access consumes
and later) can generate IDMA compatible boot code.
one additional processor cycle.
Bus Request and Bus Grant
Once an access has occurred, the latched address is automati-
The ADSP-2183 can relinquish control of the data and address
cally incremented and another access can occur.
buses to an external device. When the external device requires
Through the IDMAA register, the DSP can also specify the
access to memory, it asserts the bus request (BR) signal. If the
starting address and data format for DMA operation.
ADSP-2183 is not performing an external memory access, then
Bootstrap Loading (Booting)
it responds to the active BR input in the following processor
The ADSP-2183 has two mechanisms to allow automatic load- cycle by:
ing of the on-chip program memory after reset. The method for
" three-stating the data and address buses and the PMS, DMS,
booting after reset is controlled by the MMAP and BMODE
BMS, CMS, IOMS, RD, WR output drivers,
pins as shown in Table VI.
" asserting the bus grant (BG) signal, and
" halting program execution.
REV. C
 9
ADSP-2183
If Go Mode is enabled, the ADSP-2183 will not halt program
" The syntax is a superset ADSP-2100 Family assembly lan-
execution until it encounters an instruction that requires an
guage and is completely source and object code compatible
external memory access.
with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the ADSP-
If the ADSP-2183 is performing an external memory access
2183 s interrupt vector and reset vector map.
when the external device asserts the BR signal, then it will not
three-state the memory interfaces or assert the BG signal until
" Sixteen condition codes are available. For conditional jump,
the processor cycle after the access completes. The instruction
call, return or arithmetic instructions, the condition can be
does not need to be completed when the bus is granted. If a
checked and the operation executed in the same instruction
single instruction requires two external memory accesses, the
cycle.
bus will be granted between the two accesses.
" Multifunction instructions allow parallel execution of an
When the BR signal is released, the processor releases the BG
arithmetic instruction with up to two fetches or one write to
signal, reenables the output drivers and continues program
processor memory space during a single instruction cycle.
execution from the point where it stopped.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The bus request feature operates at all times, including when
The ADSP-2183 has on-chip emulation support and an ICE-
the processor is booting and when RESET is active.
Port, a special set of pins that interface to the EZ-ICE. These
The BGH pin is asserted when the ADSP-2183 is ready to
features allow in-circuit emulation without replacing the target
execute an instruction, but is stopped because the external bus
system processor by using only a 14-pin connection from the
is already granted to another device. The other device can re-
target system to the EZ-ICE. Target systems must have a 14-pin
lease the bus by deasserting bus request. Once the bus is re-
connector to accept the EZ-ICE s in-circuit probe, a 14-pin plug.
leased, the ADSP-2183 deasserts BG and BGH and executes
The ICE-Port interface consists of the following ADSP-2183 pins:
the external memory access.
EBR EBG ERESET
Flag I/O Pins
EMS EINT ECLK
The ADSP-2183 has eight general purpose programmable in-
ELIN ELOUT EE
put/output flag pins. They are controlled by two memory
mapped registers. The PFTYPE register determines the direc- These ADSP-2183 pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
tion, 1 = output and 0 = input. The PFDATA register is used to
read and write the values on the pins. Data being read from a except during emulation, and do not require pull-up or pull-
pin configured as an input is synchronized to the ADSP-2183 s down resistors. The traces for these signals between the ADSP-
2183 and the connector must be kept as short as possible, no
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset. longer than three inches.
In addition to the programmable flags, the ADSP-2183 has five The following pins are also used by the EZ-ICE:
fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and FL2.
BR BG
FL0-FL2 are dedicated output flags. FLAG_IN and FLAG_OUT
RESET GND
are available as an alternate configuration of SPORT1.
The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the ADSP-2183 in the target system. This causes the
INSTRUCTION SET DESCRIPTION
processor to use its ERESET, EBR and EBG pins instead of the
The ADSP-2183 assembly language instruction set has an
RESET, BR and BG pins. The BG output is three-stated.
algebraic syntax that was designed for ease of coding and read-
These signals do not need to be jumper-isolated in your system.
ability. The assembly language, which takes full advantage of
the processor s unique architecture, offers the following benefits: The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The ribbon cable is 10 inches in
" The algebraic syntax eliminates the need to remember cryptic
length with one end fixed to the EZ-ICE. The female plug is
assembler mnemonics. For example, a typical arithmetic add
plugged onto the 14-pin connector (a pin strip header) on the
instruction, such as AR = AX0 + AY0, resembles a simple
target board.
equation.
" Every instruction assembles into a single, 24-bit word that can
execute in a single instruction cycle.
 10 REV. C
ADSP-2183
Restriction: All memory strobe signals on the ADSP-2183
Target Board Connector for EZ-ICE Probe
(RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your
The EZ-ICE connector (a standard pin strip header) is shown
target system must have 10 k&! pull-up resistors connected
in Figure 7. You must add this connector to your target board
when the EZ-ICE is being used. The pull-up resistors are nec-
design if you intend to use the EZ-ICE. Be sure to allow enough
essary because there are no internal pull-ups to guarantee their
room in your system to fit the EZ-ICE probe onto the 14-pin
state during prolonged three-state conditions resulting from
connector.
typical EZ-ICE debugging sessions. These resistors may be
removed at your option when the EZ-ICE is not being used.
1 2
GND
BG
Target System Interface Signals
3 4
When the EZ-ICE board is installed, the performance on some
EBG BR
system signals changes. Design your system to be compatible
5 6
with the following system interface signal changes introduced
EBR EINT
by the EZ-ICE board:
7 8
" EZ-ICE emulation introduces an 8 ns propagation delay
KEY (NO PIN)
ELIN
between your target circuitry and the DSP on the RESET
9 10
signal.
ELOUT ECLK
" EZ-ICE emulation introduces an 8 ns propagation delay
11 12
EE
EMS between your target circuitry and the DSP on the BR signal.
13 14
" EZ-ICE emulation ignores RESET and BR when single-
ERESET
RESET
stepping.
TOP VIEW
" EZ-ICE emulation ignores RESET and BR when in Emula-
tor Space (DSP halted).
Figure 7. Target Board Connector for EZ-ICE
" EZ-ICE emulation ignores the state of target BR in certain
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
modes. As a result, the target system may take control of the
tion you must remove Pin 7 from the header. The pins must
DSP s external memory bus only if bus grant (BG) is asserted
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
by the EZ-ICE board s DSP.
ing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
Target Architecture File
probe plug. Pin strip headers are available from vendors such as
The EZ-ICE software lets you load your program in its linked
3M, McKenzie, and Samtec.
(executable) form. The EZ-ICE PC program can not load
sections of your executable located in boot pages (by the
Target Memory Interface
linker). With the exception of boot page 0 (loaded into PM
For your target system to be compatible with the EZ-ICE emu-
RAM), all sections of your executable mapped into boot pages
lator, it must comply with the memory interface guidelines
are not loaded.
listed below.
Write your target architecture file to indicate that only PM
PM, DM, BM, IOM and CM
RAM is available for program storage, when using the EZ-ICE
Design your Program Memory (PM), Data Memory (DM),
software s loading feature. Data can be loaded to PM RAM or
Byte Memory (BM), I/O Memory (IOM), and Composite
DM RAM.
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in the DSP s data sheet. The performance of the
EZ-ICE may approach published worst case specification for
some memory access timing requirements and switching
characteristics.
Note: If your target does not meet the worst case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. De-
pending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing require-
ments within published limits.
REV. C
 11
ADSP-2183 SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
K Grade B Grade
Parameter Min Max Min Max Unit
VDD Supply Voltage 3.0 3.6 3.0 3.6 V
TAMB Ambient Operating Temperature 0 +70  40 +85 °C
ELECTRICAL CHARACTERISTICS
K/B Grades
Parameter Test Conditions Min Typ Max Unit
VIH Hi-Level Input Voltage1, 2 @ VDD = max 2.0 V
VIL Lo-Level Input Voltage1, 3 @ VDD = min 0.4 V
VOH Hi-Level Output Voltage1, 4, 5 @ VDD = min
IOH =  0.5 mA 2.4 V
@ VDD = min
IOH =  100 µA6 VDD  0.3 V
VOL Lo-Level Output Voltage1, 4, 5 @ VDD = min
IOL = 2 mA 0.4 V
IIH Hi-Level Input Current3 @ VDD = max
VIN = VDD max 10 µA
IIL Lo-Level Input Current3 @ VDD = max
VIN = 0 V 10 µA
IOZH Three-State Leakage Current7 @ VDD = max
VIN = VDD max8 10 µA
IOZL Three-State Leakage Current7 @ VDD = max
VIN = 0 V8 8 µA
IDD Supply Current (Idle)9, 10 @ VDD = 3.3
TAMB = +25°C
tCK = 19 ns11 10 mA
tCK = 25 ns11 9mA
tCK = 30 ns11 8mA
tCK = 34.7 ns11 6mA
IDD Supply Current (Dynamic)10, 12 @ VDD = 3.3
TAMB = +25°C
tCK = 19 ns11 44 mA
tCK = 25 ns11 35 mA
tCK = 30 ns11 30 mA
tCK = 34.7 ns11 26 mA
CI Input Pin Capacitance3, 6, 13 @ VIN = 2.5 V
fIN = 1.0 MHz
TAMB = +25°C8 pF
CO Output Pin Capacitance6, 7, 13, 14 @ VIN = 2.5 V
fIN = 1.0 MHz
TAMB = +25°C8 pF
NOTES
1
Bidirectional pins: D0 D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD0 IAD15, PF0 PF7.
12
Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, PWD, IRQL0, IRQL1, IRQE, IS, IRD, IWR, IAL.
13
Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, IS, IAL, IRD, IWR, IRQL0, IRQL1, IRQE, PWD.
14
Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, IACK, PWDACK, A0 A13, DT0, DT1, CLKOUT, FL2-0.
15
Although specified for TTL outputs, all ADSP-2183 outputs are CMOS-compatible and will drive to V and GND, assuming no dc loads.
DD
16
Guaranteed but not tested.
17
Three-statable pins: A0 A13, D0 D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, IAD0 IAD15, PF0 PF7.
18
0 V on BR, CLKIN Active (to force three-state condition).
19
Idle refers to ADSP-2183 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V or GND.
DD
10
Current reflects device operating with no output loads.
11
VIN = 0.4 V and 2.4 V. For typical figures for supply currents, refer to Power Dissipation section.
12
IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are
1
type 2 and type 6, and 20% are idle instructions.
13
Applies to LQFP package type and Mini-BGA.
14
Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
 12 REV. C
ADSP-2183
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .  0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . .  0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . .  0.5 V to VDD + 0.5 V
Operating Temperature Range (Ambient) . . . .  40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .  65°C to +150°C
Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . . +280°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
WARNING!
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2183 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
ESD SENSITIVE DEVICE
recommended to avoid performance degradation or loss of functionality.
TIMING PARAMETERS
GENERAL NOTES
MEMORY TIMING SPECIFICATIONS
Use the exact timing information given. Do not attempt to
The table below shows common memory device specifications
derive parameters from the addition or subtraction of others.
and the corresponding ADSP-2183 timing parameters, for your
While addition or subtraction would yield meaningful results for
convenience.
an individual device, the values given in this data sheet reflect
Memory ADSP-2183 Timing
statistical variations and worst cases. Consequently, you cannot
Device Timing Parameter
meaningfully add up parameters to derive longer times.
Specification Parameter Definition
TIMING NOTES
Address Setup to tASW A0 A13, xMS Setup before
Switching Characteristics specify how the processor changes its
Write Start WR Low
signals. You have no control over this timing circuitry external
Address Setup to tAW A0 A13, xMS Setup before
to the processor must be designed for compatibility with these
Write End WR Deasserted
signal characteristics. Switching characteristics tell you what the
Address Hold Time tWRA A0 A13, xMS Hold after
processor will do in a given circumstance. You can also use switch-
WR Deasserted
ing characteristics to ensure that any timing requirement of a
Data Setup Time tDW Data Setup before WR
device connected to the processor (such as memory) is satisfied.
High
Timing Requirements apply to signals that are controlled by cir- Data Hold Time tDH Data Hold after WR High
cuitry external to the processor, such as the data input for a read
OE to Data Valid tRDD RD Low to Data Valid
operation. Timing requirements guarantee that the processor
Address Access Time tAA A0 A13, xMS to Data Valid
operates correctly with other devices.
xMS = PMS, DMS, BMS, CMS, IOMS.
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONS
tCK is defined as 0.5tCKI. The ADSP-2183 uses an input clock
with a frequency equal to half the instruction rate: a 16.67 MHz
input clock (which is equivalent to 60 ns) yields a 30 ns proces-
sor cycle (equivalent to 33 MHz). tCK values within the range of
0.5tCKI period should be substituted for all relevant timing pa-
rameters to obtain the specification value.
Example: tCKH = 0.5tCK  7 ns = 0.5 (34.7 ns)  7 ns = 10.35 ns
REV. C
 13
ADSP-2183
Parameter Min Max Unit
Clock Signals and Reset
Timing Requirements:
tCKI CLKIN Period 38 100 ns
tCKIL CLKIN Width Low 15 ns
tCKIH CLKIN Width High 15 ns
Switching Characteristics:
tCKL CLKOUT Width Low 0.5tCK  7 ns
tCKH CLKOUT Width High 0.5tCK  7 ns
tCKOH CLKIN High to CLKOUT High 0 20 ns
Control Signals
Timing Requirement:
tRSP RESET Width Low 5tCK1 ns
NOTE
1
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
tCKI
tCKIH
CLKIN
tCKIL
tCKOH
tCKH
CLKOUT
tCKL
Figure 8. Clock Signals
Parameter Min Max Unit
Interrupts and Flag
Timing Requirements:
tIFS IRQx, FI, or PFx Setup before CLKOUT Low 1, 2, 3, 4 0.25tCK + 15 ns
tIFH IRQx, FI, or PFx Hold after CLKOUT High 1, 2, 3, 4 0.25tCK ns
Switching Characteristics:
tFOH Flag Output Hold after CLKOUT Low5 0.5tCK  7 ns
tFOD Flag Output Delay from CLKOUT Low5 0.5tCK + 6 ns
NOTES
1
If IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the User s Manual for further information on interrupt servicing.)
2
Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.
3
IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.
4
PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.
5
Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.
tFOD
CLKOUT
tFOH
FLAG
OUTPUTS
tIFH
IRQx
FI
PFx
tIFS
Figure 9. Interrupts and Flags
 14 REV. C
ADSP-2183
Parameter Min Max Unit
Bus Request Bus Grant
Timing Requirements:
tBH BR Hold after CLKOUT High1 0.25tCK + 2 ns
tBS BR Setup before CLKOUT Low1 0.25tCK + 17 ns
Switching Characteristics:
tSD CLKOUT High to xMS, 0.25tCK + 10 ns
RD, WR Disable
tSDB xMS, RD, WR
Disable to BG Low 0 ns
tSE BG High to xMS,
RD, WR Enable 0 ns
tSEC xMS, RD, WR
Enable to CLKOUT High 0.25tCK  4 ns
tSDBH xMS, RD, WR
Disable to BGH Low2 0ns
tSEH BGH High to xMS,
RD, WR Enable2 0ns
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.
1
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User s Manual, Third Edition, for BR/BG cycle relationships.
2
BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
tBH
CLKOUT
BR
tBS
CLKOUT
PMS, DMS
BMS, RD
tSD
WR tSEC
BG
tSDB
tSE
BGH
tSDBH
tSEH
Figure 10. Bus Request Bus Grant
REV. C
 15
ADSP-2183
Parameter Min Max Unit
Memory Read
Timing Requirements:
tRDD RD Low to Data Valid 0.5tCK  8 + w ns
tAA A0 A13, xMS to Data Valid 0.75tCK  10.5 + w ns
tRDH Data Hold from RD High 0 ns
Switching Characteristics:
tRP RD Pulsewidth 0.5tCK  5 + w ns
tCRD CLKOUT High to RD Low 0.25tCK  2 0.25tCK + 7 ns
tASR A0 A13, xMS Setup before RD Low 0.25tCK  4 ns
tRDA A0 A13, xMS Hold after RD Deasserted 0.25tCK  3 ns
tRWR RD High to RD or WR Low 0.5tCK  5 ns
w = wait states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0  A13
DMS, PMS,
BMS, IOMS,
CMS
tRDA
RD
tASR
tRP
tRWR
tCRD
D
tRDD tRDH
tAA
WR
Figure 11. Memory Read
 16 REV. C
ADSP-2183
Parameter Min Max Unit
Memory Write
Switching Characteristics:
tDW Data Setup before WR High 0.5tCK  7 + w ns
tDH Data Hold after WR High 0.25tCK  2 ns
tWP WR Pulsewidth 0.5tCK  5 + w ns
tWDE WR Low to Data Enabled 0 ns
tASW A0 A13, xMS Setup before WR Low 0.25tCK  4 ns
tDDR Data Disable before WR or RD Low 0.25tCK  4 ns
tCWR CLKOUT High to WR Low 0.25tCK  2 0.25 tCK + 7 ns
tAW A0 A13, xMS, Setup before WR Deasserted 0.75tCK  9 + w ns
tWRA A0 A13, xMS Hold after WR Deasserted 0.25tCK  3 ns
tWWR WR High to RD or WR Low 0.5tCK  5 ns
w = wait states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
CLKOUT
A0 A13
DMS, PMS,
BMS, CMS,
IOMS
tWRA
WR
tWWR
tASW tWP
tAW
tDH tDDR
tCWR
D
tDW
tWDE
RD
Figure 12. Memory Write
REV. C
 17
ADSP-2183
Parameter Min Max Unit
Serial Ports
Timing Requirements:
tSCK SCLK Period 38 ns
tSCS DR/TFS/RFS Setup before SCLK Low 4 ns
tSCH DR/TFS/RFS Hold after SCLK Low 7 ns
tSCP SCLKIN Width 15 ns
Switching Characteristics:
tCC CLKOUT High to SCLKOUT 0.25tCK 0.25tCK + 10 ns
tSCDE SCLK High to DT Enable 0 ns
tSCDV SCLK High to DT Valid 15 ns
tRH TFS/RFSOUT Hold after SCLK High 0 ns
tRD TFS/RFSOUT Delay from SCLK High 15 ns
tSCDH DT Hold after SCLK High 0 ns
tTDE TFS (Alt) to DT Enable 0 ns
tTDV TFS (Alt) to DT Valid 14 ns
tSCDD SCLK High to DT Disable 15 ns
tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid 15 ns
CLKOUT
tCC tCC
tSCK
SCLK
tSCP
tSCS tSCH tSCP
DR
TFSIN
RFSIN
tRD
tRH
RFSOUT
TFSOUT
tSCDD
tSCDV
tSCDH
tSCDE
DT
tTDE
tTDV
TFS
ALTERNATE
FRAME MODE
tRDV
RFS
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)
Figure 13. Serial Ports
 18 REV. C
ADSP-2183
Parameter Min Max Unit
IDMA Address Latch
Timing Requirements:
tIALP Duration of Address Latch1, 2 10 ns
tIASU IAD15 0 Address Setup before Address Latch End2 5ns
tIAH IAD15 0 Address Hold after Address Latch End2 2ns
tIKA IACK Low before Start of Address Latch1 0ns
tIALS Start of Write or Read after Address Latch End2, 3 3ns
NOTES
1
Start of Address Latch = IS Low and IAL High.
2
End of Address Latch = IS High or IAL Low.
3
Start of Write or Read = IS Low and IWR Low or IRD Low.
IACK
tIKA
IAL
tIALP
IS
tIASU tIAH
IAD15 0
tIALS
IRD OR
IWR
Figure 14. IDMA Address Latch
REV. C
 19
ADSP-2183
Parameter Min Max Unit
IDMA Write, Short Write Cycle
Timing Requirements:
tIKW IACK Low before Start of Write1 0ns
tIWP Duration of Write1, 2 15 ns
tIDSU IAD15 0 Data Setup before End of Write2, 3, 4 5ns
tIDH IAD15 0 Data Hold after End of Write2, 3, 4 2ns
Switching Characteristic:
tIKHW Start of Write to IACK High 15 ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
End of Write = IS High or IWR High.
3
If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH.
4
If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.
tIKW
IACK
tIKHW
IS
tIWP
IWR
tIDH
tIDSU
IAD15 0 DATA
Figure 15. IDMA Write, Short Write Cycle
 20 REV. C
ADSP-2183
Parameter Min Max Unit
IDMA Write, Long Write Cycle
Timing Requirements:
tIKW IACK Low before Start of Write1 0ns
tIKSU IAD15 0 Data Setup before IACK Low2, 3 0.5tCK + 10 ns
tIKH IAD15 0 Data Hold after IACK Low2, 3 2ns
Switching Characteristics:
tIKLW Start of Write to IACK Low4 1.5tCK ns
tIKHW Start of Write to IACK High 15 ns
NOTES
1
Start of Write = IS Low and IWR Low.
2
If Write Pulse ends before IACK Low, use specifications tIDSU, tIDH.
3
If Write Pulse ends after IACK Low, use specifications tIKSU, tIKH.
4
This is the earliest time for IACK Low from Start of Write. For IDMA Write Cycle relationships, please refer to the ADSP-21xx Family User s Manual, Third Edition.
tIKW
IACK
tIKHW
tIKLW
IS
IWR
tIKSU
tIKH
DATA
IAD15 0
Figure 16. IDMA Write, Long Write Cycle
REV. C
 21
ADSP-2183
Parameter Min Max Unit
IDMA Read, Long Read Cycle
Timing Requirements:
tIKR IACK Low before Start of Read1 0ns
tIRP Duration of Read 15 ns
Switching Characteristics:
tIKHR IACK High after Start of Read1 15 ns
tIKDS IAD15 0 Data Setup before IACK Low 0.5tCK  7 ns
tIKDH IAD15 0 Data Hold after End of Read2 0ns
tIKDD IAD15 0 Data Disabled after End of Read2 10 ns
tIRDE IAD15 0 Previous Data Enabled after Start of Read 0 ns
tIRDV IAD15 0 Previous Data Valid after Start of Read 15 ns
tIRDH1 IAD15 0 Previous Data Hold after Start of Read (DM/PM1)3 2tCK  5 ns
tIRDH2 IAD15 0 Previous Data Hold after Start of Read (PM2)4 tCK  5 ns
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
3
DM read or first half of PM read.
4
Second half of PM read.
IACK
tIKHR
tIKR
IS
tIRP
IRD
tIKDS tIKDH
tIRDE
PREVIOUS READ
IAD15 0
DATA DATA
tIRDV
tIKDD
tIRDH
Figure 17. IDMA Read, Long Read Cycle
 22 REV. C
ADSP-2183
Parameter Min Max Unit
IDMA Read, Short Read Cycle
Timing Requirements:
tIKR IACK Low before Start of Read1 0ns
tIRP Duration of Read 15 ns
Switching Characteristics:
tIKHR IACK High after Start of Read1 15 ns
tIKDH IAD15 0 Data Hold after End of Read2 0ns
tIKDD IAD15 0 Data Disabled after End of Read2 10 ns
tIRDE IAD15 0 Previous Data Enabled after Start of Read 0 ns
tIRDV IAD15 0 Previous Data Valid after Start of Read 15 ns
NOTES
1
Start of Read = IS Low and IRD Low.
2
End of Read = IS High or IRD High.
IACK
tIKR
tIKHR
IS
tIRP
IRD
tIKDH
tIRDE
PREVIOUS
IAD15 0
DATA
tIRDV tIKDD
Figure 18. IDMA Read, Short Read Cycle
REV. C
 23
ADSP-2183
OUTPUT DRIVE CURRENTS PINT = internal power dissipation from Power vs. Frequency
Figure 19 shows typical I-V characteristics for the output drivers graph (Figure 20).
of the ADSP-2183. The curves represent the current drive
(C × VDD2 × f ) is calculated for each output:
capability of the output drivers as a function of output voltage.
100
# of
75 Pins × C × VDD2 × f
50
Address, DMS 8 × 10 pF × 3.32 V × 33.3 MHz = 29.0 mW
25 Data Output, WR 9 × 10 pF × 3.32 V × 16.67 MHz = 16.3 mW
3.6V,  40°C
RD 1 × 10 pF × 3.32 V × 16.67 MHz = 1.8 mW
0 3.3V, +25°C
CLKOUT 1 × 10 pF × 3.32 V × 33.3 MHz = 3.6 mW
3.0V, +85°C
 25
50.7 mW
 50
3.0V, +85°C
 75
Total power dissipation for this example is PINT + 50.7 mW.
3.3V, +25°C
 100
3.6V,  40°C
2183 POWER, INTERNAL1, 3, 4
 125
220
 150
205
 175
190
184mW
 200
175
0 0.75 1.50 2.25 3.00 3.75 4.50 5.25
VDD = 3.6V
SOURCE VOLTAGE  V
160
150mW
Figure 19. Typical Drive Currents 145
VDD = 3.3V
130
1000
110mW
120mW
115
VDD = 3.0V
90mW
100
VDD = 3.6V
85 72mW
VDD = 3.3V
70
100
VDD = 3.0V
28 32 36 40 44 48 52
1/tCK  MHz
POWER, IDLE1, 2, 3
50
45
10
38mW
40
VDD = 3.6V
35
30mW
30 27mW
VDD = 3.3V
25
20mW
0
085 24mW
25 55
20
TEMPERATURE  °C
VDD = 3.0V
15
NOTES:
15mW
1. REFLECTS ADSP-2183 OPERATION IN LOWEST POWER MODE.
10
(SEE "SYSTEM INTERFACE" CHAPTER OF THE ADSP-2100 FAMILY
5
USER'S MANUAL FOR DETAILS.)
2. CURRENT REFLECTS DEVICE OPERATING WITH NO INPUT LOADS. 0
28 32 36 40 44 48 52
1/tCK  MHz
Figure 20. Power-Down Supply Current (Typical)
POWER, IDLE n MODES3
32
POWER DISSIPATION 30mW
30 IDLE
To determine total power dissipation in a specific application,
28
the following equation should be applied for each output:
26
C × VDD2 × f
24
22
C = load capacitance, f = output switching frequency.
20
20mW
18
Example:
16
In an application where external data memory is used and no
13.8mW
14
IDLE (16)
other outputs are active, power dissipation is calculated as
11mW
IDLE (128)
12
follows:
13mW
10
10.6mW
Assumptions:
8
28 32 36 40 44 48 52
1/tCK  MHz
" External data memory is accessed every cycle with 50% of the
VALID FOR ALL TEMPERATURE GRADES.
address pins switching.
1
POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2
" External data memory writes occur every other cycle with IDLE REFERS TO ADSP-2183 STATE OF OPERATION DURING EXECUTION OF IDLE
INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
50% of the data pins switching.
3
TYPICAL POWER DISSIPATION AT 3.3V VDD AND 25 C EXCEPT WHERE SPECIFIED.
4
IDD MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL
" Each address and data pin has a 10 pF total load at the pin.
MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1,4,5,12,13,14),
30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS.
" The application operates at VDD = 3.3 V and tCK = 30.0 ns.
Total Power Dissipation = PINT + (C × VDD2 × f )
Figure 21. Power vs. Frequency
 24 REV. C
SOURCE CURRENT  mA
CURRENT (LOG SCALE) 

A
ADSP-2183
CAPACITIVE LOADING is calculated. If multiple pins (such as the data bus) are dis-
Figures 22 and 23 show the capacitive loading characteristics of abled, the measurement value is that of the last pin to stop
the ADSP-2183. driving.
25
T = +85 C INPUT
1.5V 1.5V
VDD = 3.0V OR
OUTPUT
20
Figure 24. Voltage Reference Levels for AC Measure-
ments (Except Output Enable/Disable)
15
Output Enable Time
Output pins are considered to be enabled when they have made
10
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
5
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
0
the data bus) are enabled, the measurement value is that of the
0 20 40 60 80 100 120 140 160 180 200
CL  pF first pin to start driving.
Figure 22. Typical Output Rise Time vs. Load Capacitance,
REFERENCE
CL (at Maximum Ambient Operating Temperature)
SIGNAL
tMEASURED
18
tENA
16 tDIS
VOH VOH
(MEASURED) (MEASURED)
14
VOH (MEASURED)  0.5V
2.0V
12
OUTPUT
1.0V
VOL (MEASURED) +0.5V
10
VOL VOL
tDECAY
8
(MEASURED) (MEASURED)
6
OUTPUT STARTS
OUTPUT STOPS
4
DRIVING
DRIVING
2
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE
THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V.
NOMINAL
 2
Figure 25. Output Enable/Disable
 4
 6
IOL
0 40 80 120 160 200
CL  pF
Figure 23. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
TO
Temperature)
+1.5V
OUTPUT
PIN
50pF
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they have
IOH
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out-
Figure 26. Equivalent Device Loading for AC Measure-
put disable time (tDIS) is the difference of tMEASURED and tDECAY,
ments (Including All Fixtures)
as shown in the Output Enable/Disable diagram. The time is the
interval from when a reference signal reaches a high or low ENVIRONMENTAL CONDITIONS
voltage level to when the output voltages have changed by 0.5 V Ambient Temperature Rating:
from the measured output high or low voltage. The decay time,
TAMB = TCASE  (PD × ¸CA)
tDECAY, is dependent on the capacitive load, CL, and the current
TCASE = Case Temperature in °C
load, iL, on the output pin. It can be approximated by the fol-
PD = Power Dissipation in W
lowing equation:
¸CA = Thermal Resistance (Case-to-Ambient)
CL " 0.5V ¸JA = Thermal Resistance (Junction-to-Ambient)
tDECAY =
¸JC = Thermal Resistance (Junction-to-Case)
iL
from which
Package JA JC CA
tDIS = tMEASURED  tDECAY
LQFP 50°C/W 2°C/W 48°C/W
Mini-BGA 70.7°C/W 7.4°C/W 63.3°C/W
REV. C
 25
RISE TIME (0.4V  2.4V)  ns
OR HOLD  ns
VALID OUTPUT DELAY
ADSP-2183
128-Lead LQFP Package Pinout
IAL 1 102
GND
PIN 1
PF3 2 101 D23
IDENTIFIER
PF2 3 100 D22
PF1 4 99 D21
PF0 5 98 D20
WR 6 97 D19
RD 7 96 D18
8 95 D17
IOMS
9 94
BMS D16
10 93
DMS D15
CMS 11 92 GND
GND 12 91 VDD
VDD 13 90 GND
14 89
PMS D14
A0 15 88 D13
A1 16 87 D12
A2 17 86 D11
A3 18 85 D10
ADSP-2183
A4 19 84 D9
TOP VIEW
83
A5 20 (Not to Scale) D8
A6 21 82 D7
A7 22 81 D6
XTAL 23 80 D5
CLKIN 24 79 GND
GND 25 78 D4
CLKOUT 26 77 D3
GND 27 76 D2
VDD 28 75 D1
A8 29 74 D0
A9 30 73 VDD
A10 31 72 BG
A11 32 71
EBG
A12 33 70
BR
A13 34 69
EBR
IRQE 35 68
EINT
MMAP 36 67 ELIN
37 66 ELOUT
PWD
IRQ2 38 65 ECLK
 26 REV. C
DD
IS
IRD
IWR
PF6
IAD9
IAD7
IAD6
IAD11
IAD14
IAD15
IAD13
108 IAD12
111
114
110 IAD10
115 V
121 IAD1
116 GND
122 IAD0
117 IAD5
112 IAD8
113
109
128
107
106
105
104
120 IAD2
118 IAD4
127 GND
126 PF4
125 PF5
124
123 PF7
119 IAD3
103
47
51
61
43
59
63
56
57
41
45
46
55
58
50
54
40
62
52
42
DD
EE
64
FL0
FL1 48
FL2 49
V
DT0
DR0
53
EMS
BGH
GND 44
GND
TFS0
IACK
RFS0
IRQL0
IRQL1
DR1/FI
SCLK0
SCLK1
60
DT1/F0
RESET
BMODE
39
ERESET
PWDACK
RFS1/
IRQ0
TFS1/
IRQ1
ADSP-2183
LQFP Pin Configurations
LQFP Pin LQFP Pin LQFP Pin LQFP Pin
Number Name Number Name Number Name Number Name
1 IAL 33 A12 65 ECLK 97 D19
2 PF3 34 A13 66 ELOUT 98 D20
3 PF2 35 IRQE 67 ELIN 99 D21
4 PF1 36 MMAP 68 EINT 100 D22
5 PF0 37 PWD 69 EBR 101 D23
6 WR 38 IRQ2 70 BR 102 GND
7 RD 39 BMODE 71 EBG 103 IWR
8 IOMS 40 PWDACK 72 BG 104 IRD
9 BMS 41 IACK 73 VDD 105 IAD15
10 DMS 42 BGH 74 D0 106 IAD14
11 CMS 43 VDD 75 D1 107 IAD13
12 GND 44 GND 76 D2 108 IAD12
13 VDD 45 IRQL0 77 D3 109 IAD11
14 PMS 46 IRQL1 78 D4 110 IAD10
15 A0 47 FL0 79 GND 111 IAD9
16 A1 48 FL1 80 D5 112 IAD8
17 A2 49 FL2 81 D6 113 IAD7
18 A3 50 DT0 82 D7 114 IAD6
19 A4 51 TFS0 83 D8 115 VDD
20 A5 52 RFS0 84 D9 116 GND
21 A6 53 DR0 85 D10 117 IAD5
22 A7 54 SCLK0 86 D11 118 IAD4
23 XTAL 55 DT1/F0 87 D12 119 IAD3
24 CLKIN 56 TFS1/IRQ1 88 D13 120 IAD2
25 GND 57 RFS1/IRQ0 89 D14 121 IAD1
26 CLKOUT 58 GND 90 GND 122 IAD0
27 GND 59 DR1/FI 91 VDD 123 PF7
28 VDD 60 SCLK1 92 GND 124 PF6
29 A8 61 ERESET 93 D15 125 PF5
30 A9 62 RESET 94 D16 126 PF4
31 A10 63 EMS 95 D17 127 GND
32 A11 64 EE 96 D18 128 IS
REV. C
 27
ADSP-2183
144-Lead Mini-BGA Package Pinout
(Bottom View)
12 11 10 9 8 7 6 5 4 3 2 1
GND GND IWR IAD14 IAD10 IAD6 GND IAD2 PF6 GND IS IAL A
D21 D23 IRD IAD15 IAD11 VDD GND IAD1 PF5 GND PF3 PF1
B
D17 D20 D22 IAD13 IAD8 VDD IAD0 PF4 PF2 WR PF0 RD
C
GND D15 D18 D19 D16 IAD9 IAD5 PF7 IOMS GND DMS GND
D
D14 GND VDD GND GND IAD7 CMS IAD3 BMS A0 VDD VDD E
D10 D11 D13 D12 IAD12 D8 IAD4 PMS A3 A4 A1 A2 F
D6 D5 D9 D4 D7 DT0 A7 A8 A6 GND A5 XTAL G
H
GND D2 GND D0 D3 DT1 IRQL0 VDD GND GND GND CLKIN
VDD VDD D1 BG RFS1 SCLK0 IRQL1 VDD VDD A10 VDD CLKOUT J
EBG BR EBR ERESET SCLK1 TFS1 TFS0 FL2 PWDACK A11 A12 A9 K
L
EINT ELOUT ELIN RESET GND DR0 FL0 GND IACK IRQE MMAP A13
M
ECLK EE EMS DR1 GND RFS0 FL1 GND BGH BMODE IRQ2 PWD
 28 REV. C
ADSP-2183
Mini-BGA Pin Configurations
Ball # Name Ball # Name Ball # Name Ball # Name
A01 IAL D01 GND G01 XTAL K01 A9
A02 IS D02 DMS G02 A5 K02 A12
A03 GND D03 GND G03 GND K03 A11
A04 PF6 D04 IOMS G04 A6 K04 PWDACK
A05 IAD2 D05 PF7 G05 A8 K05 FL2
A06 GND D06 IAD5 G06 A7 K06 TFS0
A07 IAD6 D07 IAD9 G07 DT0 K07 TFS1
A08 IAD10 D08 D16 G08 D7 K08 SCLK1
A09 IAD14 D09 D19 G09 D4 K09 ERESET
A10 IWR D10 D18 G10 D9 K10 EBR
A11 GND D11 D15 G11 D5 K11 BR
A12 GND D12 GND G12 D6 K12 EBG
B01 PF1 E01 VDD H01 CLKIN L01 A13
B02 PF3 E02 VDD H02 GND L02 MMAP
B03 GND E03 A0 H03 GND L03 IRQE
B04 PF5 E04 BMS H04 GND L04 IACK
B05 IAD1 E05 IAD3 H05 VDD L05 GND
B06 GND E06 CMS H06 IRQL0 L06 FL0
B07 VDD E07 IAD7 H07 DT1 L07 DR0
B08 IAD11 E08 GND H08 D3 L08 GND
B09 IAD15 E09 GND H09 D0 L09 RESET
B10 IRD E10 VDD H10 GND L10 ELIN
B11 D23 E11 GND H11 D2 L11 ELOUT
B12 D21 E12 D14 H12 GND L12 EINT
C01 RD F01 A2 J01 CLKOUT M01 PWD
C02 PF0 F02 A1 J02 VDD M02 IRQ2
C03 WR F03 A4 J03 A10 M03 BMODE
C04 PF2 F04 A3 J04 VDD M04 BGH
C05 PF4 F05 PMS J05 VDD M05 GND
C06 IAD0 F06 IAD4 J06 IRQL1 M06 FL1
C07 VDD F07 D8 J07 SCLK0 M07 RFS0
C08 IAD8 F08 IAD12 J08 RFS1 M08 GND
C09 IAD13 F09 D12 J09 BG M09 DR1
C10 D22 F10 D13 J10 D1 M10 EMS
C11 D20 F11 D11 J11 VDD M11 EE
C12 D17 F12 D10 J12 VDD M12 ECLK
REV. C
 29
ADSP-2183
OUTLINE DIMENSIONS
Dimensions given in mm and (inches).
128-Lead Metric Plastic Thin Quad Flatpack (LQFP)
(ST-128)
16.20 (0.638)
16.00 (0.630)
1.60 (0.063) 15.80 (0.622)
MAX
0.75 (0.030)
0.60 (0.024)
128 103
0.50 (0.020) 1 102
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.08 (0.003)
38 65
MAX LEAD
39 64
COPLANARITY
0.15 (0.006)
0.27 (0.011)
0.50 (0.020)
0.05 (0.002)
BSC 0.22 (0.009)
LEAD PITCH
0.17 (0.007)
1.45 (0.057)
LEAD WIDTH
1.40 (0.055)
1.35 (0.053) 14.10 (0.555)
14.00 (0.551)
13.90 (0.547)
NOTES:
THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08
(0.0032) FROM ITS IDEAL POSITION WHEN MEASURED IN THE
LATERAL DIRECTION.
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED
 30 REV. C
22.20 (0.874)
22.00 (0.866)
21.80 (0.858)
20.10 (0.792)
20.00 (0.787)
19.90 (0.783)
ADSP-2183
OUTLINE DIMENSIONS
Dimensions given in mm and (inches).
144-Lead Mini-BGA Package Pinout
(CA-144)
0.404 (10.25)
0.394 (10.00) SQ
0.384 (9.75) 12 11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
0.346
E
0.404 (10.25) (8.80)
F
BSC
0.394 (10.00) SQ
TOP VIEW
G
0.384 (9.75)
H
0.031
J
(0.80)
K
BSC
L
M
0.031 (0.80) BSC
DETAIL A
0.346 (8.80) BSC
0.067 (1.70) MAX
0.010 DETAIL A
(0.25)
NOM
0.034 (0.85) MIN
NOTE
THE ACTUAL POSITION OF THE BALL POPULATION
0.010 (0.25) MIN
IS WITHIN 0.006 (0.150) OF ITS IDEAL POSITION
RELATIVE TO THE PACKAGE EDGES. THE ACTUAL
POSITION OF EACH BALL IS WITHIN 0.003 (0.08) OF
0.022 (0.55)
0.005 SEATING
ITS IDEAL POSITION RELATIVE TO THE BALL POPULATION.
(0.12) PLANE
0.020 (0.50)
MAX
0.018 (0.45)
BALL DIAMETER
ORDERING GUIDE
Ambient Instruction
Temperature Rate Package Package
Part Number Range (MHz) Description Option
ADSP-2183KST-115 0°C to +70°C 28.8 128-Lead LQFP ST-128
ADSP-2183BST-115  40°C to +85°C 28.8 128-Lead LQFP ST-128
ADSP-2183KST-133 0°C to +70°C 33.3 128-Lead LQFP ST-128
ADSP-2183BST-133  40°C to +85°C 33.3 128-Lead LQFP ST-128
ADSP-2183KST-160 0°C to +70°C 40 128-Lead LQFP ST-128
ADSP-2183BST-160  40°C to +85°C 40 128-Lead LQFP ST-128
ADSP-2183KST-210 0°C to +70°C 52 128-Lead LQFP ST-128
ADSP-2183KCA-210 0°C to +70°C 52 144-Lead Mini-BGA CA-144
REV. C
 31
C00184b 0 7/00 (rev. C)
PRINTED IN U.S.A.