8080katalog1

8080A

8080 INSTRUCTION SET

Summary of Processor Instructions

Instruclion Code| 11 Clock|2| Mnemomc Deserlption_D? D5 D5 D4 D3 O2 D| 0q Cycles

■OK. L0A0. AND STORĘ

M0V»1 r2	Move register to register	0	1	D	D	D	S	s	s	5
M0V M i	Move register to memory	0	1	1	1	0	s	S	s	7
pr.M	Move memory to register	0	1	D	D	D	1	1	0	7
MVIr	Move iminediate register	0	0	D	0	D	1	1	0	7
iniM	Move immediate memory	0	0	1	1	0	1	1	0	10
Ud B	Load immediate register Pair B & C	0	0	0	0	0	0	0	1	10
1X1D	Load immediate register Pair D & E	0	0	0	1	0	0	0	1	10
LXIH	Load immediate register Pair H & L	0	0	1	0	0	0	0	1	10
I STAX U	Storę A indirect	0	0	0	0	0	0	1	0	7
L STAX 0	Storę A indirect	0	0	0	1	0	0	1	0	7
[ L0AX 8	Load A indirect	0	0	0	0	1	0	1	0	7
‘ LDAX D	Load A indirect	0	0	0	1	1	0	1	0	7
1 STA	Storę A direct	0	0	1	1	0	0	1	0	13
[ IDA	Load A direct	0	0	1	1	1	0	1	0	13
1 SHLD	Storę H & L drrecl	0	0	1	0	0	0	1	0	16
IHLD	Load H & L direct	0	0	1	0	1	0	1	0	16
XCHG	Exchange 0 & E H & L Registers	1	1	1	0	1	0	1	1	4
STACK OPS
PUSH B	Push registei Pair B & Ć on stack	1	1	0	0	0	1	0	1	11
PUSHD	Push register Pair D & E on stack	1	1	0	1	0	1	0	1	11
PUSH H	Push register Pair H & L on stack	1	1	1	0	0	1	0	1	11
PUSH PSW	Push A and Flags on stack	1	1	1	1	0	1	0	1	11
POP 8	Pop register Pair 8 & C ofl stack	1	1	0	0	0	0	0	1	10
POPO	Pop register Pair D & E off stack	1	I	0	1	0	0	0	1	10
POP H	Pop register Pair H & L off stack	1	1	1	0	0	0	0	1	10
POP PSW	Pop A and Flags off stack	1	1	1	1	0	0	0	1	10
XTHL	Exchange top of stack. H & L	1	1	1	0	0	0	1	1	18
SPHL	H & L to stack pointer	1	1	1	1	1	0	0	1	5
LXISP	Load immediate stack pointer	0	0	1	1	0	0	0	1	10
^: INK SP	Increment stack pointer	0	0	1	1	0	0	1	1	5
i DCXSP	Decrement stack pointer	0	0	1	1	1	0	1	1	5
JUMP
JMP	Jump unconditional	1	1	0	0	0	0	1	1	10
JC	Jump on carry	1	1	0	1	1	0	1	0	10
JNC	Jump on no carry	1	1	0	1	0	0	1	0	10
JZ	Jump on zero	1	1	0	0	1	0	1	0	10
JNZ	Jump on no zero	1	1	0	0	0	0	1	0	10
JP	Jump on positive	1	1	1	1	0	0	1	0	10
JM	Jump on minus	1	1	1	1	1	0	1	0	10
JPE	Jump on panty even	1	1	1	0	1	0	1	0	10

Instruction Code[i) Clock(2]

Mnemonic	Deserlption	07	tle	05	04	D3	Dz	Dl	Do	Cycles
JPO	Jump on parity odd	1	1	1	0	0	0	1	0	10
PCHL CALL	H & L to program counter	1	1	1	0	1	0	0	1	5
CALL	Cali unconditional	1	1	0	0	1	1	0	1	17
CC	Cali on carry	1	1	0	1	1	1	0	0	11/17
CNC	Cali on no carry	1	1	0	1	0	1	0	0	11/17
CZ	Cali on zero	1	1	0	0	1	1	a	0	11/17
CNZ	Cali on no zero	1	t	0	0	0	1	0	0	11/17
CP	Cali on positive	1	1	1	1	0	1	0	0	11/17
CM	Cali on minus	1	1	1	1	1	1	0	0	11/17
CPE	Cali on pariiy even	1	1	1	0	1	1	0	0	11/17
CPO RETURN	Cali on parity odd	1	1	1	0	0	1	0	0	11/17
RET	Return	1	1	0	0	1	0	0	1	10
RC	Return on carry	1	1	0	1	1	0	0	0	5/11
RNC	Return on no cariy	1	1	0	1	0	0	0	0	5/11
RZ	Return on zero	1	1	0	0	1	0	0	0	5/11
RNZ	Return on no zero	1	1	0	0	0	0	0	0	5/11
RP	Return on posihve	1	1	1	1	0	0	0	0	5/11
RM	Return on minus	1	1	1	1	1	0	0	0	5/11
RPE	Return on parity even	1	1	1	0	1	0	0	0	5/11
RPO RESTART	Return on parity odd	1	1	1	0	0	0	0	0	5/11
RST Restart INCREMENT AND DECREMENT		1	1	A	A	A	1	1	1	11
INR r	Increment register	0	0	D	D	D	1	0	0	5
DCR r	Oecrement register	0	0	D	D	D	1	0	1	5
INR M	Increment memory	0	0	1	1	0	1	0	0	10
DCR M	Decrement memory	0	0	1	1	0	1	0	1	10
INX B	Increment B & C registers	0	0	0	0	0	0	1	l	5
INX D	Increment D & E registers	0	0	0	1	0	0	1	1	5
IN X H	Increment H & L registers	0	0	1	0	0	0	1	1	5
DCX B	Decrement B & C	0	0	0	0	1	0	1	1	5
DCX D	Decrement D & E	0	0	0	1	1	0	1	1	5
DCX H ADD	Decrement H & L	0	0	1	0	1	0	1	1	5
ADD r	Add register to A	1	c	0	0	0	s	S	s	4
ADC r	Add register to A with carry	1	0	0	0	1	S	S	s	4
ADD M	Add memory to A	1	0	0	0	0	1	1	0	7
ADC M	Add memory to A with carry	1	0	0	0	1	1	1	g	7
ADI	Add immediate to A	1	1	0	0	0	1	1	0	7
ACI	Add immediate to A with carry	1	1	0	0	1	1	1	0	7
DAD B	Add B & C to H & L	0	0	0	0	1	0	0	1	10
DAD D	Ado D & E to H & L	0	0	0	1	1	0	0	1	10
DAD H	Add H & L to H & L	0	0	1	0	1	0	0	1	10
DAD SP	Add stack pointer to H & L	0	0	1	1	1	0	0	1	10

"Ali mnemonics copyright ‘Intel Corporation 1977

NOTES 1 DDDor SSS B 000. C 001 0 010 E 011 H 100 L 101 Memory 110 A 111

2 Two possible cycle times '6/12) mdicate insiriicliori cycles dependent on condition llags

10-17