Xilinx Design Summary system Project Status Project File: system.xmp Implementation State: New Module Name: system Errors:   Product Version:EDK 14.2 Warnings:     XPS Reports [-] Report NameGenerated ErrorsWarningsInfos Platgen Log FileŚr 12. cze 09:51:49 2013X 2 Errors (0 new)1 Warning (1 new)20 Infos (0 new) Simgen Log File     BitInit Log File     System Log FileŚr 12. cze 09:51:49 2013      XPS Synthesis Summary (estimated values) [-] ReportGeneratedFlip Flops UsedLUTs UsedBRAMS UsedErrors system_seven_seg_bright_control_0_wrapperŚr 12. cze 09:51:46 2013   5 system_clock_generator_0_wrapperŚr 12. cze 09:51:39 2013   0 system_axi4lite_0_wrapperŚr 12. cze 09:47:55 201396198 0 system_debug_module_wrapperŚr 12. cze 09:47:39 2013131142 0 system_microblaze_0_wrapperŚr 12. cze 09:47:29 201315701583 0 system_microblaze_0_bram_block_wrapperŚr 12. cze 09:46:50 2013  40 system_microblaze_0_d_bram_ctrl_wrapperŚr 12. cze 09:46:44 201326 0 system_microblaze_0_dlmb_wrapperŚr 12. cze 09:46:38 20131  0 system_microblaze_0_i_bram_ctrl_wrapperŚr 12. cze 09:46:33 201326 0 system_microblaze_0_ilmb_wrapperŚr 12. cze 09:46:27 20131  0 system_proc_sys_reset_0_wrapperŚr 12. cze 09:46:21 20136955 0   Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos Translation Report      Map Report      Place and Route Report      Post-PAR Static Timing Report      Bitgen Report        Secondary Reports [-] Report NameStatusGenerated Date Generated: 06/12/2013 - 09:51:49