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VLSI LAB MANUAŁ

Part A

Sl.no.	Programs	Page No.	Remarks
1	Timing verification withgate level simulationof an lnverter (Sample program)
2	Timing verification withgate level simulationof a Buffer
3	Timing verrf ication withgate level simulationof Transmission Gate
4(a)	Timing verification with gate level simulation of AND gate
4(b)	Timing verification with gate level simulation of OR gate
4(c)	Timing verifk:ation with gate level simulation of XOR gate
4(d)	Timing verif ication with gate level simulation of XN0R gate
4(e)	Timing verification withgate level simulationof NANDgate
4(0	Timing verif ication withgate level simulationof NOR gate
5(a)	Timing verification with gate level simulation of SR flip-flop
5(b)	Timing verification withgate level simulationof D flip-flop
5(c)	Timing verification withgate level simulation of JK flip-flop
5(d)	Timing verification withgate level simulationof MS flip-flop
5(e)	Timing verif ication with gate level simulation of T flip-flop
6	Timing verifk:ation with gate level simulation of Parallel Adder
7(a)	Timing verification withgate level simulationof Synchronous Counter
7(b)	Timing verif ication with gate level simulation of an Asynchronous Counter
8	Timing verification withgate level simulationof Successive Approximation Register (SAR)

Part B

SI.No.	Programs	PageNo.	Remarks
1.	Design of an im/erter using analog design flow

Bearys Institute of Technology, Dept. of ECE, Mangaluru Page 3