IRF730
Data Sheet January 2002
5.5A, 400V, 1.000 Ohm, N-Channel Power Features
MOSFET
" 5.5A, 400V
This is an N-Channel enhancement mode silicon gate power
" rDS(ON) = 1.000&!
field effect transistor. It is an advanced power MOSFET
" Single Pulse Avalanche Energy Rated
designed, tested, and guaranteed to withstand a specified
level of energy in the breakdown avalanche mode of
" SOA is Power Dissipation Limited
operation. All of these power MOSFETs are designed for
" Nanosecond Switching Speeds
applications such as switching regulators, switching
convertors, motor drivers, relay drivers, and drivers for high
" Linear Transfer Characteristics
power bipolar switching transistors requiring high speed and
" High Input Impedance
low gate drive power. These types can be operated directly
" Related Literature
from integrated circuits.
- TB334  Guidelines for Soldering Surface Mount
Formerly developmental type TA17414.
Components to PC Boards
Ordering Information
Symbol
PART NUMBER PACKAGE BRAND
D
IRF730 TO-220AB IRF730
NOTE: When ordering, use the entire part number.
G
S
Packaging
JEDEC TO-220AB
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
�2002 Fairchild Semiconductor Corporation IRF730 Rev. B
IRF730
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
IRF730 UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 400 V
Drain to Gate Voltage (RGS = 20k&!) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . .VDGR 400 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 5.5 A
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 3.5 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 22 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ą20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 75 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6 W/oC
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . EAS 300 mJ
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 C
Maximum Temperature for Soldering
o
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . .TL 300 C
o
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 260 C
CAUTION: Stresses above those listed in  Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250�A, VGS = 0V (Figure 10) 400 - - V
Gate Threshold Voltage VGS(TH) VDS = VGS, ID = 250�A 2.0 - 4.0 V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - 25 �A
VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC - - 250 �A
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX, VGS = 10V (Figure 7) 5.5 - - A
Gate to Source Leakage Current IGSS VGS = ą20V - - ą100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = 3.0A, VGS = 10V (Figure 8, 9) - 0.800 1.000 &!
Forward Transconductance (Note 2) gfs VDS e" 10V, ID = 3.3A (Figure 12) 2.9 4.4 - S
Turn-On Delay Time td(ON) VDD = 200V, ID H" 5.5A, RGS = 12&!, RL = 35&! - 10 17 ns
Rise Time tr MOSFET Switching Times are Essentially - 20 29 ns
Independent of Operating Temperature
Turn-Off Delay Time td(OFF) - 35 56 ns
Fall Time tf - 15 24 ns
Total Gate Charge Qg(TOT) VGS = 10V, ID = 5.5A, VDS = 0.8 x Rated BVDSS, - 20 35 nC
(Gate to Source + Gate to Drain) Ig(REF) = 1.5mA, (Figure 14)
Gate to Source Charge Qgs Gate Charge is Essentially Independent of - 3.0 - nC
Operating Temperature
Gate to Drain  Miller Charge Qgd - 10 - nC
Input Capacitance CISS VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) - 600 - pF
Output Capacitance COSS - 150 - pF
Reverse Transfer Capacitance CRSS - 40 - pF
Internal Drain Inductance LD Measured From the Modified MOSFET - 3.5 - nH
Contact Screw on Tab to Symbol Showing the
Center of Die Internal Device
Inductances
Measured From the Drain - 4.5 - nH
D
Lead, 6mm (0.25in) From
Package to Center of Die
LD
Internal Source Inductance LS Measured From the - 7.5 - nH
Source Lead, 6mm G
LS
(0.25in) From Header to
Source Bonding Pad
S
o
Thermal Resistance Junction to Case R�JC - - 1.67 C/W
o
Thermal Resistance Junction to Ambient R�JA Free Air Operation - - 80 C/W
�2002 Fairchild Semiconductor Corporation IRF730 Rev. B
IRF730
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current ISD Modified MOSFET Symbol - - 5.5 A
D
Pulse Source to Drain Current ISDM Showing the Integral - - 22 A
Reverse P-N Junction
(Note 3)
Rectifier
G
S
Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 5.5A, VGS = 0V (Figure 13) - - 1.6 V
Reverse Recovery Time trr TJ = 25oC, ISD = 5.5A, dISD/dt = 100A/�s 140 300 660 ns
Reverse Recovery Charge QRR TJ = 25oC, ISD = 5.5A, dISD/dt = 100A/�s 0.93 2.1 4.3 �C
NOTES:
2. Pulse test: pulse width d"d" 300�s, duty cycle d"d" 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 50V, starting TJ = 25oC, L = 17mH, RG = 25&!, peak IAS = 5.5A.
Typical Performance Curves Unless Otherwise Specified
1.2
6
1.0
4
0.8
0.6
2
0.4
0.2
0
0
25 50 75 100 125 150
0 50 100 150
TC, CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE
10
1 0.5
0.2
PDM
0.1
0.1
0.05
t1
0.02
t2
0.01
NOTES:
DUTY FACTOR: D = t1/t2
SINGLE PULSE
PEAK TJ = PDM x Z�JC + TC
0.01
10-5 10-4 10-3 10-2 10-1 100 101
t1, RECTANGULAR PULSE DURATION (s)
FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE
�2002 Fairchild Semiconductor Corporation IRF730 Rev. B
D
I , DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
o
�
JC
Z
, TRANSIENT
THERMAL IMPEDANCE ( C/W)
IRF730
Typical Performance Curves Unless Otherwise Specified (Continued)
10
100
OPERATION IN THIS AREA
VGS = 10V
PULSE DURATION = 80�s
IS LIMITED BY rDS(ON)
VGS = 6.0V DUTY CYCLE = 0.5% MAX
8
10�s
10
6
100�s VGS = 5.5V
1ms 4
1 VGS = 5.0V
10ms
2
TC = 25oC
VGS = 4.5V
TJ = MAX RATED
DC
VGS = 4.0V
SINGLE PULSE
0.1 0
0 40 80 120 160 200
1 10 100 1000
VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
10 10
PULSE DURATION = 80�s VGS = 10V
DUTY CYCLE = 0.5% MAX
8 VGS = 6.0V
1
6
TJ = 150oC
TJ = 25oC
VGS = 5.5V
4
0.1
VGS = 5.0V
2
VDS e" 50V
VGS = 4.5V
PULSE DURATION = 80�s
VGS = 4.0V
DUTY CYCLE = 0.5% MAX
0
0.01
0 3 6912 15 02468 10
VDS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
10 3.0
PULSE DURATION = 80�s
PULSE DURATION = 80�s
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 5.5A
8 2.4
VGS = 10V
1.8
6
VGS = 20V
1.2
4
0.6
2
0
0
-40 0 40 80 120 160
0369 12 15
ID, DRAIN CURRENT (A) TJ, JUNCTION TEMPERATURE (oC)
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
VOLTAGE AND DRAIN CURRENT RESISTANCE vs JUNCTION TEMPERATURE
�2002 Fairchild Semiconductor Corporation IRF730 Rev. B
D
D
I , DRAIN CURRENT (A)
I , DRAIN CURRENT (A)
D
DR
I , DRAIN CURRENT (A)
I
, DRAIN CURRENT (A)
ON RESISTANCE
ON RESISTANCE (
&!
)
DS(ON)
r
, DRAIN TO SOURCE
NORMALIZED DRAIN TO SOURCE
IRF730
Typical Performance Curves Unless Otherwise Specified (Continued)
1.25 1500
ID = 250�A
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
1.15
1200
COSS+" H" CDS + CGD
CISS
1.05
900
COSS
0.95
600
0.85
CRSS
300
0.75
0
-40 0 40 80 120 160
110100
TJ, JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VOLTAGE vs JUNCTION TEMPERATURE
10 100
PULSE DURATION = 80�s
PULSE DURATION = 80�s
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
8
10
TJ = 25oC
6
TJ = 150oC TJ = 25oC
4
1
TJ = 150oC
2
0.1
0
0 0.4 0.8 1.2 1.6 2.0
0246810
ID, DRAIN CURRENT (A) VSD, SOURCE TO DRAIN VOLTAGE (V)
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
20
ID = 5.5A
16
VDS = 320V
VDS = 200V
12
VDS = 80V
8
4
0
0 8 16 24 32 40
Qg, GATE CHARGE (nC)
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
�2002 Fairchild Semiconductor Corporation IRF730 Rev. B
C, CAPACITANCE (pF)
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
fs
g
, TRANSCONDUCTANCE (S)
SD
I
, SOURCE TO DRAIN CURRENT (A)
GS
V
, GATE TO SOURCE VOLTAGE (V)
IRF730
Test Circuits and Waveforms
VDS
BVDSS
tP
L
VDS
IAS
VARY tP TO OBTAIN
+
VDD
RG
REQUIRED PEAK IAS
VDD
-
VGS
DUT
tP
0V IAS
0
0.01&!
tAV
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
tON tOFF
td(ON) td(OFF)
tr tf
RL VDS
90%
90%
+
VDD
10% 10%
RG
0
-
DUT 90%
VGS 50%
50%
PULSE WIDTH
10%
VGS
0
FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT
VDS
(ISOLATED
CURRENT
SUPPLY)
REGULATOR
VDD
SAME TYPE Qg(TOT)
VGS
AS DUT
12V
0.2�F Qgd
50k&!
BATTERY
0.3�F
Qgs
D
VDS
G DUT
0
Ig(REF)
S
0
VDS
Ig(REF)
IG CURRENT ID CURRENT
SAMPLING SAMPLING
RESISTOR RESISTOR 0
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
�2002 Fairchild Semiconductor Corporation IRF730 Rev. B
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Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or
This datasheet contains the design specifications for
In Design
product development. Specifications may change in
any manner without notice.
Preliminary First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete Not In Production
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that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
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