Xilinx Design Summary dzielnik Project Status (03/25/2013 - 13:45:43) Project File: cw6.xise Parser Errors: No Errors Module Name: dzielnik Implementation State: Fitted Target Device: xc2c256-6TQ144 Errors:   Product Version:ISE 14.4 Warnings:   Design Goal: Balanced Routing Results:   Design Strategy: Xilinx Default (unlocked) Timing Constraints:   Environment: System Settings Final Timing Score:      Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos Synthesis ReportCurrentPn 25. mar 13:25:46 2013    Translation ReportCurrentPn 25. mar 13:25:52 2013    Map Report      Place and Route Report      CPLD Fitter Report (Text)      Power Report      Post-PAR Static Timing Report      Bitgen Report        Secondary Reports [-] Report NameStatusGenerated Post-Fit Simulation Model Report   Date Generated: 03/25/2013 - 13:45:43