Xilinx Design Summary dzielnik Project Status Project File: wysw.xise Parser Errors: X 1 Error Module Name: dzielnik Implementation State: New Target Device: xc2c256-6TQ144 Errors:   Product Version:ISE 14.4 Warnings:   Design Goal: Balanced Routing Results:   Design Strategy: Xilinx Default (unlocked) Timing Constraints:   Environment:   Final Timing Score:      Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos Synthesis Report      Translation Report      CPLD Fitter Report (Text)      Power Report        Secondary Reports [-] Report NameStatusGenerated Post-Fit Simulation Model Report   Date Generated: 05/17/2013 - 11:18:06