Xilinx Design Summary dzielnik Project Status (05/13/2013 - 10:59:53) Project File: vhdl.xise Parser Errors: No Errors Module Name: dzielnik Implementation State: Synthesized Target Device: xc2c256-6TQ144 Errors:   Product Version:ISE 14.4 Warnings:   Design Goal: Balanced Routing Results:   Design Strategy: Xilinx Default (unlocked) Timing Constraints:   Environment:   Final Timing Score:      Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos Synthesis Report      Translation Report      Map Report      Place and Route Report      CPLD Fitter Report (Text)      Power Report      Post-PAR Static Timing Report      Bitgen Report        Secondary Reports [-] Report NameStatusGenerated Post-Fit Simulation Model Report   Date Generated: 05/13/2013 - 10:59:53