Xilinx Design Summary glowny Project Status (03/04/2013 - 13:19:29) Project File: cw1.xise Parser Errors: No Errors Module Name: glowny Implementation State: Fitted Target Device: xc2c256-6TQ144 Errors: No Errors Product Version:ISE 14.4 Warnings: 2 Warnings (0 new) Design Goal: Balanced Routing Results:   Design Strategy: Xilinx Default (unlocked) Timing Constraints:   Environment: System Settings Final Timing Score:      Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos Synthesis ReportCurrentPn 4. mar 13:25:21 201302 Warnings (0 new)0 Translation ReportCurrentPn 4. mar 13:25:27 2013000 CPLD Fitter Report (Text)CurrentPn 4. mar 13:25:30 201301 Warning (1 new)0 Power Report        Secondary Reports [-] Report NameStatusGenerated Post-Fit Simulation Model Report   Date Generated: 03/05/2013 - 08:18:51