Xilinx Design Summary glowny Project Status (06/03/2013 - 12:01:33) Project File: automat.xise Parser Errors: No Errors Module Name: glowny Implementation State: Fitted Target Device: xc2c256-6TQ144 Errors: No Errors Product Version:ISE 14.4 Warnings: 2 Warnings (0 new) Design Goal: Balanced Routing Results:   Design Strategy: Xilinx Default (unlocked) Timing Constraints:   Environment: System Settings Final Timing Score:      Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos Synthesis ReportCurrentPn 3. cze 12:01:16 201302 Warnings (0 new)0 Translation ReportCurrentPn 3. cze 12:01:22 2013000 CPLD Fitter Report (Text)CurrentPn 3. cze 12:01:26 201303 Warnings (1 new)1 Info (1 new) Power Report        Secondary Reports [-] Report NameStatusGenerated Post-Fit Simulation Model Report   Date Generated: 06/03/2013 - 12:01:33