NOT FOR NEW DESIGN
Recommended replacement —
A6818
4
5
6
7
8
9
10
11
2
3
DD
V
BB
LOAD
SUPPLY
SERIAL
DATA IN
LOGIC
SUPPLY
OUT
30
NC
44
1
SERIAL
DATA OUT
12
OUT
1
2
OUT
8
OUT
29
OUT
36
37
38
39
19
34
35
OUT
4
OUT
13
32
33
29
30
31
NC
18
19
20
21
22
ST
CLK
OUT
16
OUT
17
CLOCK
STROBE
GROUND
BLANKING
23
24
OUT
15
25
26
Dwg. PP-059-2
OUT
14
27
28
NC
OUT
18
NC
BLNK
13
14
15
16
17
OUT
42
43
V
40
41
OUT
3
OUT
2
OUT
32
OUT
31
REGISTER
LATCHES
LATCHES
REGISTER
19
Designed primarily for use with vacuum-fluorescent displays, the
UCN5818AF and UCN5818EPF smart power BiMOS II drivers combine
CMOS shift registers, data latches, and control circuitry, with bipolar high-
speed sourcing outputs and DMOS active pull-down circuitry. The high-
speed shift register and data latches allow direct interfacing with microproces-
sor LSI-based systems. A CMOS serial data output enables cascade connec-
tions in applications requiring additional drive lines. Both devices feature
60 V and -40 mA output ratings, allowing them to be used in many other
peripheral power driver applications.
These smart power drivers have been designed with BiMOS II logic for
improved data entry rates. With a 5 V supply, it will operate to at least 3.3
MHz. At 12 V, higher speeds are possible. Use of these devices with TTL
may require the use of appropriate pull-up resistors to ensure an input logic
high. All devices can be operated over the ambient temperature range of -
20
°
C to +85
°
C. The UCN5818AF is supplied in a 40-pin plastic dual in-line
package with 0.600" (15.24 mm) row spacing. A copper lead frame, reduced
supply current requirement, and low output saturation voltage permits
operation with minimum junction temperature rise. The ‘A’ package allows
all 32 outputs to be operated at -25 mA continuously over the operating
temperature range.
For high-density packaging applications, the UCN5818EPF is furnished
in a 44-lead plastic chip carrier (quad pack) for surface mounting on solder
lands with 0.050" (1.27 mm) centers. The PLCC allows -25 mA continuous
operation of all outputs simultaneously at ambient temperatures to 60
°
C.
Similar devices are available as the UCN5810AF/LWF (10 bits), UCN5811A
(12 bits), and UCN5812AF/EPF (20 bits).
UCN5818EPF
BiMOS II 32-BIT SERIAL-INPUT, LATCHED
SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
Always order by complete part number, e.g., UCN5818EPF .
FEATURES
■
60 V Source Outputs
■
High-Speed Source Drivers
■
To 3.3 MHz Data Input Rate
■
Low-Output Saturation Voltages
■
Active DMOS Pull-Downs
■
Low-Power CMOS Logic
and Latches
■
Reduced Supply Current
Requirements
■
Improved Replacements for
SN75518N/FN
ABSOLUTE MAXIMUM RATINGS
at T
A
= 25
°
C
Logic Supply Voltage, V
DD
.................... 15 V
Driver Supply Voltage, V
BB
................... 60 V
Continuous Output Current,
I
OUT
......................... -40 mA to +15 mA
Input Voltage Range,
V
IN
....................... -0.3 V to V
DD
+ 0.3 V
Package Power Dissipation, P
D
(UCN5818AF) ............................ 3.5 W*
(UCN5818EPF) ......................... 2.3 W†
Operating Temperature Range,
T
A
................................. -20
°
C to +85
°
C
Storage Temperature Range,
T
S
............................... -55
°
C to +150
°
C
* Derate at rate of 28 mW/
°
C above T
A
= +25
°
C
† Derate at rate of 18 mW/
°
C above T
A
= +25
°
C
Caution: CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
Data Sheet
26182.28D
5818-F
5818-F
32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
MOS
BIPOLAR
OUT
1
OUT
2
GROUND
Dwg. FP-013-1
OUT
3
OUT
N
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
SERIAL
DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V
DD
V
BB
LOGIC
SUPPLY
LOAD
SUPPLY
UCN5818AF
FUNCTIONAL BLOCK DIAGRAM
TYPICAL OUTPUT DRIVER
Dwg. No. A-14,219
V
OUT
BB
N
TYPICAL INPUT CIRCUIT
50
75
100
125
150
2.5
0.5
0
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN
°°°°
C
2.0
1.5
1.0
25
Dwg. GP-025B
3.0
SUFFIX 'EP', R
θ
JA
= 54
°
C/W
SUFFIX 'A', R
θ
JA
= 36
°
C/W
4
5
6
7
8
9
10
12
13
14
15
16
17
18
11
19
20
31
32
33
34
35
36
37
LOAD
SUPPLY
BB
V
OUT
2
OUT
7
OUT
8
Dwg. PP-029-4
OUT
31
OUT
30
OUT
25
23
24
25
26
27
28
29
30
SERIAL
DATA OUT
BLANKING
LOGIC
SUPPLY
39
40
SERIAL
DATA IN
STROBE
GROUND
CLOCK
CLK
ST
BLNK
OUT
9
OUT
10
OUT
15
OUT
16
OUT
24
OUT
23
OUT
22
OUT
17
LATCHES
REGISTER
REGISTER
LATCHES
2
3
38
OUT
6
OUT
1
OUT
4
OUT
3
OUT
32
1
21
22
OUT
20
OUT
18
OUT
14
OUT
19
OUT
21
OUT
11
OUT
12
OUT
13
OUT
5
OUT
29
OUT
28
OUT
27
OUT
26
DD
V
Dwg. EP-010-5
IN
V
DD
Copyright © 1988, 2002 Allegro MicroSystems, Inc.
5818-F
32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
www.allegromicro.com
ELECTRICAL CHARACTERISTICS at T
A
= + 25
°
C, V
BB
= 60 V unless otherwise noted.
Limits @ V
DD
= 5 V Limits @ V
DD
= 12 V
Characteristic
Symbol
Test Conditions
Mln.
Typ.
Max.
Min.
Typ.
Max.
Units
Output Leakage Current
I
CEX
V
OUT
= 0 V, T
A
= +70
°
C
—
-5.0
-15
—
-5.0
-15
µ
A
Output Voltage
V
OUT(1)
I
OUT
= -25 mA
58
58.5
—
58
58.5
—
V
V
OUT(0)
I
OUT
= 1 mA
—
2.0
3.0
—
—
—
V
I
OUT
= 2 mA
—
—
—
—
2.0
3.5
V
Output Pull-Down Current
I
OUT(0)
V
OUT
= 5 V to V
BB
2.0
3.5
—
—
—
—
mA
V
OUT
= 20 V to V
BB
—
—
—
8.0
13
—
mA
Input Voltage
V
IN(1)
3.5
—
5.3
10.5
—
12.3
V
V
IN(0)
-0.3
—
+0.8
-0.3
—
+0.8
V
Input Current
I
IN(1)
V
IN
= V
DD
—
0.05
0.5
—
0.1
1.0
µ
A
I
IN(0)
V
IN
= 0.8 V
—
-0.05
-0.5
—
-0.1
-1.0
µ
A
Serial Data Output Voltage
V
OUT(1)
I
OUT
= -200
µ
A
4.5
4.7
—
11.7
11.8
—
V
V
OUT(0)
I
OUT
= 200
µ
A
—
200
250
—
100
200
mV
Maximum Clock Frequency
f
clk
3.3*
—
—
—
—
—
MHz
Supply Current
I
DD(1)
All Outputs High
—
100
300
—
200
500
µ
A
I
DD(0)
All Outputs Low
—
100
300
—
200
500
µ
A
I
BB(1)
Outputs High, No Load
—
3.0
6.0
—
3.0
6.0
mA
I
BB(0)
Outputs Low
—
10
100
—
10
100
µ
A
Blanking to Output Delay
t
PHL
C
L
= 30 pF, 50% to 50%
—
2000
—
—
1000
—
ns
t
PLH
C
L
= 30 pF, 50% to 50%
—
1000
—
—
850
—
ns
Output Fall Time
t
f
C
L
= 30 pF, 90% to 10%
—
1450
—
—
650
—
ns
Output Rise Time
t
r
C
L
= 30 pF, 10% to 90%
—
650
—
—
700
—
ns
Negative current is defined as coming out of (sourcing) the specified device terminal.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
5818-F
32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
TRUTH TABLE
Serial
Shift Register Contents
Serial
Latch Contents
Output Contents
Data
Clock
Data
Strobe
Input
Input I
1
I
2
I
3
...
I
N-1
I
N
Output
Input
I
1
I
2
I
3
...
I
N-1
I
N
Blanking
I
1
I
2
I
3
... I
N-1
I
N
H
H
R
1
R
2
...
R
N-2
R
N-1
R
N-1
L
L
R
1
R
2
...
R
N-2
R
N-1
R
N-1
X
R
1
R
2
R
3
...
R
N-1
R
N
R
N
X
X
X
...
X
X
X
L
R
1
R
2
R
3
...
R
N-1
R
N
P
1
P
2
P
3
...
P
N-1
P
N
P
N
H
P
1
P
2
P
3
...
P
N-1
P
N
L
P
1
P
2
P
3
... P
N-1
P
N
X
X
X
...
X
X
H
L
L
L
... L
L
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUT-
PUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is trans-
ferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as
the STROBE is held high. Applications where
the latches are bypassed (STROBE tied high) will
require that the BLANKING input be high during
serial data entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON, the information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
TIMING REQUIREMENTS
(T
A
= +25
°
C,V
DD
= 5 V, Logic Levels are V
DD
and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . 300 ns
F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
E F
CLOCK
DATA IN
STROBE
BLANKING
OUT
N
A D
B
C
G
Dwg. No. A-12,649A
5818-F
32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
www.allegromicro.com
UCN5818AF
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
4. Supplied in standard sticks/tubes of 9 devices.
40
0.580
0.485
1
2
3
0.250
MAX
0.070
0.030
0.015
MIN
0.022
0.014
0.015
0.008
0.600
BSC
Dwg. MA-003-40 in
20
0.100
BSC
0.005
MIN
0.200
0.115
4
0.700
MAX
21
2.095
1.980
40
14.73
12.32
1
2
3
6.35
MAX
1.77
0.77
0.39
MIN
0.558
0.356
0.381
0.204
15.24
BSC
Dwg. MA-003-40 mm
20
2.54
BSC
0.13
MIN
5.08
2.93
4
17.78
MAX
21
53.2
50.3
5818-F
32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
UCN5818EPF
Dimensions in Inches
(controlling dimensions)
Dimensions in Millimeters
(for reference only)
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel.
18
28
Dwg. MA-005-44A in
0.020
MIN
0.050
BSC
1
44
0.021
0.013
INDEX AREA
2
6
7
17
29
39
40
0.695
0.685
0.032
0.026
0.319
0.291
0.319
0.291
0.180
0.165
0.695
0.685
0.656
0.650
0.656
0.650
Dwg. MA-005-44A mm
17.65
17.40
0.51
MIN
4.57
4.20
17.65
17.40
16.662
16.510
1.27
BSC
0.812
0.661
1
44
0.533
0.331
INDEX AREA
2
28
29
39
40
6
7
17
18
16.662
16.510
8.10
7.39
8.10
7.39
5818-F
32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
www.allegromicro.com
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsi-
bility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
5818-F
32-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
POWER
INTERFACE DRIVERS
Function
Output Ratings*
Part Number†
SERIAL-INPUT LATCHED DRIVERS
8-Bit (saturated drivers)
-120 mA
50 V‡
5895
8-Bit
350 mA
50 V
5821
8-Bit
350 mA
80 V
5822
8-Bit
350 mA
50 V‡
5841
8-Bit
350 mA
80 V‡
5842
8-Bit (constant-current LED driver)
75 mA
17 V
6275
8-Bit (constant-current LED driver)
120 mA
24 V
6277
8-Bit (DMOS drivers)
250 mA
50 V
6595
8-Bit (DMOS drivers)
350 mA
50 V‡
6A595
8-Bit (DMOS drivers)
100 mA
50 V
6B595
10-Bit (active pull-downs)
-25 mA
60 V
5810-F and 6810
12-Bit (active pull-downs)
-25 mA
60 V
5811
16-Bit (constant-current LED driver)
75 mA
17 V
6276
20-Bit (active pull-downs)
-25 mA
60 V
5812-F and 6812
32-Bit (active pull-downs)
-25 mA
60 V
5818-F and 6818
32-Bit
100 mA
30 V
5833
32-Bit (saturated drivers)
100 mA
40 V
5832
PARALLEL-INPUT LATCHED DRIVERS
4-Bit
350 mA
50 V‡
5800
8-Bit
-25 mA
60 V
5815
8-Bit
350 mA
50 V‡
5801
8-Bit (DMOS drivers)
100 mA
50 V
6B273
8-Bit (DMOS drivers)
250 mA
50 V
6273
SPECIAL-PURPOSE DEVICES
Unipolar Stepper Motor Translator/Driver
1.25 A
50 V‡
5804
Addressable 8-Bit Decoder/DMOS Driver
250 mA
50 V
6259
Addressable 8-Bit Decoder/DMOS Driver
350 mA
50 V‡
6A259
Addressable 8-Bit Decoder/DMOS Driver
100 mA
50 V
6B259
Addressable 28-Line Decoder/Driver
450 mA
30 V
6817
*
Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.
†
Complete part number includes additional characters to indicate operating temperature range and package style.
‡
Internal transient-suppression diodes included for inductive-load protection.
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