LIBRARY ieee ;
USE ieee.std_logic_1164.all ; ENTITY dflipflop IS
PORT ( D, Clock : IN
STD_LOGIC ;
Q
: OUT STD_LOGIC) ;
END dflipflop ;
ARCHITECTURE implementacja OF dflipflop IS
BEGIN
PROCESS ( Clock )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END implementacja;
Kod przerzutnika D z instrukcją WAIT UNTIL
LIBRARY ieee;
USE ieee.std_logic_1164.all; ENTITY dflipflop IS
PORT ( D, Clock : IN
STD_LOGIC ;
Q
: OUT
STD_LOGIC ) ;
END dflipflop ;
ARCHITECTURE implementacja OF dflipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ; Q <= D ;
END PROCESS ;
END implementacja;
Przerzutnik D z zerowaniem asynchronicznym LIBRARY ieee ;
USE ieee.std_logic_1164.all ; ENTITY dflipflop IS
PORT ( D, RST, Clock
: IN
STD_LOGIC ;
Q
: OUT
STD_LOGIC) ;
END dflipflop ;
ARCHITECTURE implementacja OF dflipflop IS
BEGIN
PROCESS ( RST, Clock )
BEGIN
IF RST = '0' THEN
Q <= '0' ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END implementacja;
D
Q
D
Q
Q
Q
3
3
D
2
2
1
1
D0
0
FF
FF
FF
3
2
1
FF0
CLK
RST (Clear)
Przerzutnik D z zerowaniem synchronicznym LIBRARY ieee ;
USE ieee.std_logic_1164.all ; ENTITY dflipflop IS
PORT ( D, RST, Clock
: IN
STD_LOGIC ;
Q
: OUT
STD_LOGIC) ;
END dflipflop ;
ARCHITECTURE implementacja OF dflipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF RST = '0' THEN
Q <= '0' ;
ELSE
Q <= D ;
END IF ;
END PROCESS ;
END implementacja;
LIBRARY ieee ; USE ieee.std_logic_1164.all ; Rejestr
STD_LOGIC_VECTOR (3 DOWNTO 0) ENTITY dflipflop IS
PORT ( D
: IN
STD_LOGIC ;
RST, Clock
: IN
STD_LOGIC ;
Q
: OUT
STD_LOGIC) ;
END dflipflop ;
Rejestr
ARCHITECTURE implementacja OF dflipflop IS
BEGIN
PROCESS ( RST, Clock )
BEGIN
IF RST = '0' THEN
Q <= '0' ;
Q <= ”0000”
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END implementacja;
Rejestr czterobitowy z zerowaniem asynchronicznym
LIBRARY ieee ;
USE ieee.std_logic_1164.all ; ENTITY reg4 IS
PORT ( D
: IN
STD_LOGIC_VECTOR(3 DOWNTO 0) ; RST, Clock
: IN
STD_LOGIC ;
Q
: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END reg4 ;
ARCHITECTURE implementacja OF reg4 IS
BEGIN
PROCESS ( RST, Clock )
BEGIN
IF RST = '0' THEN
Q <= "0000" ; ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END implementacja ;
LIBRARY ieee ; USE ieee.std_logic_1164.all ; GENERIC (N: INTEGER := 8); N
ENTITY reg4 IS
PORT ( D
: IN
STD_LOGIC_VECTOR(3 DOWNTO 0) ; RST, Clock
: IN
STD_LOGIC ;
Q
: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END reg4 ;
N
ARCHITECTURE implementacja OF reg4 IS
BEGIN
PROCESS ( RST, Clock )
BEGIN
IF RST = '0' THEN
Q <= "0000" ; Q <= (OTHERS => ‘0’
ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END implementacja ;
Rejestr n-bitowy z zerowaniem LIBRARY ieee ;
asynchronicznym
USE ieee.std_logic_1164.all ; ENTITY regn IS
GENERIC ( N : INTEGER := 8 ) ; PORT ( D
: IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; RST, Clock
: IN
STD_LOGIC ;
Q
: OUT
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ;
ARCHITECTURE implementacja OF regn IS
BEGIN
PROCESS ( RST, Clock )
BEGIN
IF RST = '0' THEN
Q <= (OTHERS => '0') ; ELSIF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END implementacja ;
Przerzutnik D z multiplekserem LIBRARY ieee ;
USE ieee.std_logic_1164.all ; ENTITY muxdff IS
PORT ( D0, D1, Sel, Clock : IN
STD_LOGIC ;
Q
: OUT
STD_LOGIC ) ;
END muxdff ;
ARCHITECTURE implementacja OF muxdff IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Sel = '0' THEN
Q <= D0 ;
ELSE
Q <= D1 ;
END IF ;
END PROCESS ;
END implementacja ;
Rejestr przesuwający z wpisem równoległym Wyjścia równoległe
Q3
Q2
Q1
Q0
D
Q
D
Q
D
Q
D
Q
Q
Q
Q
Q
Wejście
szeregowe
Shift/Load
Wejścia równoległe
Clock
Rejestr przesuwający LIBRARY ieee ;
USE ieee.std_logic_1164.all ; ENTITY shift4 IS
PORT ( R
: IN
STD_LOGIC_VECTOR(3 DOWNTO 0) ; L, Sin, Clock : IN
STD_LOGIC ;
Q
: BUFFER
STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END shift4 ;
ARCHITECTURE Structure OF shift4 IS
COMPONENT muxdff
PORT ( D0, D1, Sel, Clock : IN
STD_LOGIC ;
Q
: OUT
STD_LOGIC ) ;
END COMPONENT ;
BEGIN
Stage3: muxdff PORT MAP ( Sin, R(3), L, Clock, Q(3) ) ; Stage2: muxdff PORT MAP ( Q(3), R(2), L, Clock, Q(2) ) ; Stage1: muxdff PORT MAP ( Q(2), R(1), L, Clock, Q(1) ) ; Stage0: muxdff PORT MAP ( Q(1), R(0), L, Clock, Q(0) ) ; END Structure ;
Inna specyfikacja rejestru LIBRARY ieee ;
USE ieee.std_logic_1164.all ; przesuwającego
ENTITY shift4 IS
PORT ( R
: IN
STD_LOGIC_VECTOR(3 DOWNTO 0) ; Clock :
IN
STD_LOGIC
;
L, Sin
: IN
STD_LOGIC ;
Q
: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END shift4 ;
ARCHITECTURE implementacja OF shift4 IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF L = '1' THEN
Q <= R ;
ELSE
Q(0) <= Q(1) ;
Q(1) <= Q(2);
Q(2) <= Q(3) ;
Q(3) <= Sin ;
END IF ;
END PROCESS ;
END implementacja ;
Rejestr przesuwający w innej wersji LIBRARY ieee ;
USE ieee.std_logic_1164.all ; ENTITY shift4 IS
PORT ( R
: IN
STD_LOGIC_VECTOR(3 DOWNTO 0) ; Clock :
IN
STD_LOGIC
;
L, Sin
: IN
STD_LOGIC ;
Q
: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END shift4 ;
ARCHITECTURE implementacja OF shift4 IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF L = '1' THEN
Q <= R ;
ELSE
Q(3) <= Sin ;
Q(2) <= Q(3) ;
Q(1) <= Q(2);
Q(0) <= Q(1) ;
END IF ;
END PROCESS ;
END implementacja ;
LIBRARY ieee ; N-bitowy rejestr przesuwający USE ieee.std_logic_1164.all ; ENTITY shiftn IS
w prawo
GENERIC ( N : INTEGER := 8 ) ; PORT (
R
: IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Clock :
IN
STD_LOGIC
;
L, Sin
: IN
STD_LOGIC ;
Q
: BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END shiftn ;
ARCHITECTURE implementacja OF shiftn IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF L = '1' THEN
Q <= R ;
ELSE
Genbits: FOR i IN 0 TO N-2 LOOP
Q(i) <= Q(i+1) ;
END LOOP ;
Q(N-1) <= Sin ;
END IF ;
END PROCESS ;
END implementacja ;
Rejestr z sygnałem zezwolenia LIBRARY ieee ;
USE ieee.std_logic_1164.all ; ENTITY regn IS
GENERIC ( N : INTEGER := 8 ) ; PORT ( R
: IN
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Rin, Clock
: IN
STD_LOGIC ;
Q
: OUT
STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ; END regn ;
ARCHITECTURE implementacja OF regn IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ; IF Rin = '1' THEN
Q <= R ;
END IF ;
END PROCESS ;
END implementacja ;