Karolak Karol

Grupa: I6A1N2

Programowanie układów logicznych

Projekt:
Licznik czterobitowy pracujący w kodzie
dziesiętnobinarnym 8421

Schemat logiczny

Opis sieci w standardzie PLDSHELL

CHIP licznik 22V10

PIN T

PIN Q1

PIN Q2

PIN Q3

PIN Q4

EQUATIONS

Q1.CLKF = T

Q2.CLKF = T

Q3.CLKF = T

Q4.CLKF = T

Q1 := /Q1

Q2 := Q2 * /Q1 + /Q2 * Q1

Q3 := Q3 * /Q1 + Q3 * /Q2 + /Q3 * Q2 * Q1

Q4 := Q4 * /Q1 + Q4 * /Q2 + Q4 * /Q3 + /Q4 * Q3 * Q2 * Q1

SIMULATION

SETF /T

PRLDF /Q1 /Q2 /Q3 /Q4

FOR X:=0 TO 9 DO

BEGIN

CLOCKF T

END

PRLDF /Q1 /Q2 /Q3 /Q4

CLOCKF T

FOR X:=0 TO 4 DO

BEGIN

CLOCKF T

END

Raport

ALTERA Logic Optimizing Compiler Utilization Report LICZNIK.rpt

FIT Release [ 5.0 ] SID [ 306 ]

***** Design implemented successfully

OPTIONS

EXPAND = ON

INVERSION = ON

DT_SYNTHESIS = OFF

MINIMIZATION = ON

FITTER_PINS = KEEP

SECURITY = OFF

; ( part was 22V10 before conversion )

CHIP LICZNIK EP22V10

PIN 1 T

PIN [17:14] Q[1:4]

EQUATIONS

Q1.D := /Q1

Q1.CLKF = T

Q1.RSTF = GND

Q1.SETF = GND

Q1.TRST = VCC

Q2.D := Q2 * /Q1

+ /Q2 * Q1

Q2.CLKF = T

Q2.RSTF = GND

Q2.SETF = GND

Q2.TRST = VCC

Q3.D := Q3 * /Q1

+ Q3 * /Q2

+ /Q3 * Q2 * Q1

Q3.CLKF = T

Q3.RSTF = GND

Q3.SETF = GND

Q3.TRST = VCC

Q4.D := Q4 * /Q1

+ Q4 * /Q2

+ Q4 * /Q3

+ /Q4 * Q3 * Q2 * Q1

Q4.CLKF = T

Q4.RSTF = GND

Q4.SETF = GND

Q4.TRST = VCC

SIMULATION

SETF /T

PRLDF /Q1 /Q2 /Q3 /Q4

FOR X := 0 TO 9 DO

BEGIN

CLOCKF T

END

PRLDF /Q1 /Q2 /Q3 /Q4

CLOCKF T

FOR X := 0 TO 4 DO

BEGIN

CLOCKF T

END

LICZNIK.rpt

ALTERA Logic Optimizing Compiler Utilization Report LICZNIK.rpt

***** Design implemented successfully

EP22V10

- - - - -

T -| 1 24|- Vcc

Gnd -| 2 23|- Gnd

Gnd -| 3 22|- Gnd

Gnd -| 4 21|- Gnd

Gnd -| 5 20|- Gnd

Gnd -| 6 19|- Gnd

Gnd -| 7 18|- Gnd

Gnd -| 8 17|- Q1

Gnd -| 9 16|- Q2

Gnd -|10 15|- Q3

Gnd -|11 14|- Q4

GND -|12 13|- Gnd

- - - - -

CMOS Device: ground unused inputs and I/Os Gnd = unused input or I/O pin.

RESERVED = Leave pins unconnected on board. N.C. = unconnected pins

LICZNIK.rpt

**OUTPUTS**

Name Pin Resource MCell PTerms | Sync Clock

Q1 17 RORF 3 1/14 | T

Q2 16 RORF 2 2/12 | T

Q3 15 RORF 1 3/10 | T

Q4 14 RORF 0 4/ 8 | T

**INPUTS**

Name Pin Resource MCell PTerms | Sync Clock

T 1 INP - - | -

**UNUSED RESOURCES**

Name Pin Resource MCell PTerms

- 2 INPUT - -

- 3 INPUT - -

- 4 INPUT - -

- 5 INPUT - -

- 6 INPUT - -

- 7 INPUT - -

- 8 INPUT - -

- 9 INPUT - -

- 10 INPUT - -

- 11 INPUT - -

- 13 INPUT - -

- 18 MCELL 4 16

- 19 MCELL 5 16

- 20 MCELL 6 14

- 21 MCELL 7 12

- 22 MCELL 8 10

- 23 MCELL 9 8

**PART UTILIZATION**

4/10 MacroCells (40%), 22% of used Pterms Filled

1/12 Input Pins (8%)

PTerms Used 8%

**RESOURCE MNEMONICS**

INP = Pin Input to Logic Array

RORF = D-Register pin Output, Register Feedback

Macrocell Interconnection Cross Reference LICZNIK.rpt

FEEDBACKS: M M M M

0 0 0 0

0 1 2 3

Q4 ....... RORF @M0 -> * . . . @14

Q3 ....... RORF @M1 -> * * . . @15

Q2 ....... RORF @M2 -> * * * . @16

Q1 ....... RORF @M3 -> * * * * @17

INPUTS:

T ........ INP @1 -> * * * *

Q Q Q Q

4 3 2 1

. = not connected x = no connection possible

* = signal feeds cell ? = error, unable to fit

Wynik symulacji

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