Wejścia
(4-bitowy naturalny kod dwójkowy)
0 |
3—0' |
1 |
3—1 |
A \ |
=>—2 |
3 |
3-3 |
B 4 |
3-4 |
c 41 * |
3-5 |
6 |
3-6 |
D 7 |
3—-7 |
8 |
3-8 |
9 |
3-9 |
0 |
^8 |
1 |
3—.9 |
A 2 |
3-W |
3 |
3-11 |
B 42 4 |
3-12 |
c s |
3-13 |
n $ |
3-14 |
D 7 |
3-15. |
8 | |
9 |
Wyjścia \kad TzW)
Rys. 4.412. Konwerter 4-bitowego kodu dwójkowego na kod 1 z 16 zbudowany z dekoderów scalonych 42
a) schemat logiczny,
b) tablica ilustrująca działanie układu
Dekoder 42 |
Dekoder 42+inweńer | |||||||||
D |
C |
B |
A |
Wy |
D |
c |
B |
A |
Wy | |
0 |
Q |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
8 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
0 |
0 |
1 |
9 |
2 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
- |
3 |
0 |
0 |
1 |
1 |
3 |
1 |
0 |
/ |
1 |
- |
4 |
0 |
1 |
0 |
0 |
4 |
1 |
1 |
0 |
0 |
- |
5 |
0 |
1 |
0 |
1 |
5 |
1 |
7 |
0 |
1 |
- |
6 |
0 |
1 |
1 |
0 |
6 |
1 |
1 |
1 |
0 |
- |
7 |
0 |
1 |
1 |
1 |
7 |
1 |
1 |
1 |
1 |
- |
8 |
1 |
0 |
0 |
Q |
8 |
0 |
0 |
0 |
0 |
0 |
9 |
1 |
0 |
0 |
1 |
9 |
0 |
0 |
0 |
1 |
1 |
10 |
1 |
0 |
1 |
0 |
- |
0 |
0 |
1 |
0 |
1 |
11 |
1 |
0 |
1 |
1 |
- |
0 |
0 |
1 |
1 |
3 |
12 |
1 |
1 |
0 |
0 |
- |
0 |
1 |
0 |
0 |
4 |
13 |
1 |
1 |
0 |
1 |
- |
0 |
1 |
0 |
1 |
5 |
14 |
1 |
1 |
1 |
0 |
- |
0 |
1 |
1 |
0 |
6 |
15 |
1 |
1 |
1 |
1 |
- |
0 |
1 |
1 |
1 |
7 |
A >
Strob>
A >-
B >-C >-
>-£5-
A |
0 1 |
B |
2 3 |
c <* |
4 5 |
6 | |
D |
7 8 |
9 |
Rys. 4.413. Schemat logiczny demultipleksera 16-wyjściowego zbudowanego z dwu dekoderów scalonych 42
Strob. >—
Rys. 4.414. Schemat logiczny demultipleksera 10-wyjściowego zbudowanego w oparciu o dekoder scalony 42