File: e:\projekty_vhdl\ps\dz\src\zap.vhd
1
2
3
4
5
6
7
8
9
10 11 12
13
14
15
16
17
18
19
20 21 22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
-- Title : zap
-- Design : dz
Author : LABO5
Compa ny : WTPN
--- File -- Generated ..... From
- m
Description :
zap. vhd
Thu Apr 2 11:14:38 2009 interface deseription file Itf2Vhdl ver. 1.20
--{{ Section belotv this comment is automatically maintained and may be overwritten - {en tity {zap} a rch i tecture {zap } }
library IEEE;
use IEEE.STD_LOGIC_l164.all;
entity zap is port (
a : in INTEGER rangę 0 to 50; b : in INTEGER rangę 0 to 80; c : out INTEGER rangę 0 to 130; d : out INTEGER rangę 0 to 4000
end zap;
--}} End o£ automatically maintained section
architecture zap of zap is begin
c<= a + b; d<= a * b;
end zap;
1