skanuj0008

File: e:\projekty_vhdl\ps\dz\src\3.vhd

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3    Titla    :    \3\

4    -- Design    :    dz

5    ...... Aut hor    :    LABO5

6    Company    :    W7PN

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■File    :    3.vhd

Generated ;    Thu Apr    2 10:46:07    2009

....... From    :    interface deser iptibn    file

...... By    :    It£2Vhdl.    ver. 1.20

-- Description :

-{{ Section below this comment is automatically maintained and may be overwrittetn ■- - {en t i ty {\ 3 \} arch i tecture {13 \ } }

library IEEE;

use IEEE.STD_LOGIC_l164.all;

entity \3\ is port (

x 1 : x2 : x3 : x4 : yl : y2 : );

end \3\;

in STD_LOGIC; in STD_LOGIC; in STD_LOGIC; in STD_LOGIC; out STD_LOGIC; out STD LOGIC

- ■■■ |} En d of aut om a t i cal 1 y mai n ta i ned sect. i o n

architecture \3\ of \3\ is begin

y2<= ( x4 or not x3 or x2) and ( not x4 or not x2 or xl); yl<= ( not x4 and x2 and xl ) or ( x4 and not x3 and not xl

end \3\;

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