♦ ColdFire processor core
—Variable-lengtli RISC, clock-multipliedVersion 4 microprocessor core
— Implementatioii of Revision B oftlie ColdFire instructionsetarcliitecture(ISA), wliicli leveragestlie 68Kprogramming model
— Two independent decoupled pipelines: four-stage instruction fetcli pipeline (IFP) andfive-stage operand execution pipeline (OEP)
— Ten-instruction FIFObuffer provides decouplingbetween tlie pipelines*
— Limited superscalar design acliieves performance levels close to dual-issue performance
— Programmable two-level brancli acceleration meclianism witli an 8-elitry brancli ca che plus a 128-e litry predictiontable for increased pei*formance
— 32-bit i lite r 11 a 1 address bus supporting4 Gbytes of linear address space
— 32-bit data bus
—16 user-accessible, 32-bit-wide, general-purpose registers
— Supervisor/user modes for system protection
—Vectorbase register to relocate exception-vectortable
— Optimized for liigli-level language constructs