♦ 16-Kbyte instruction ca clie, 8-Kbyte data caclie
— Four-way set-associative organization
— Operates at liiglier processor core frequency
— Provides pipelined, single-cycleaccessto critical codę and data
— Data caclie supports write-througli and copybackinodes
— Four-entry, 32-bit storę b uff er to iniprove performance of operand writes ♦ Two, 2-Kbyte SRAMs
— Pro gra 111111 ab le location anywliere witliin 4-Gbyte linear address space
— Higlier core-frequency operation
— Pipelined, single-cycle access to critical codę or data
— Eacli błock mappableto eitliertlie instruction or data operand bus