4382790094

4382790094



Seat No.:___ Enrolment No.____

GUJARAT TECHNOLOGICAL UNIVERSITY

BE - SEMESTER-YI(NEW) -EXAM1NATI()N -SUMMER 2019 Subject Codę:2160709    Datę:21/05/2019

Subject NameiEnibedded & VLS1 Design

Time: 10:30 AM TO 01:00 PM    Total Marks: 70

Instmctions:

1.    A tleni pt ail ijucstions.

2.    Make suitablc assumptinns wherever necessary.

3.    Figur es to the right indieate fuli marks.

Q.l (a) Give classifications of embedded systems in brief.    03

(b)    Explain depletion region of nMOS.

(c)    What is EDLC? Explain different phases of Embedded product DeveIopment life cycle.

Q.2    (a) Explain Embedded firmware.

(b)    Explain watch dog timer and real time clock in brief.

(c)    Explain the fundamental issues of hardware software co-design in brief.

OR

(c) Explain overview of VLSI design methodologies.

Q.3    (a) What do you mean by sensors and actuators?

(b)    Explain tlie concept of modularity and locality in brief.

(c)    Explain fabrication steps of nMOS in detial

OR

Q.3    (a) What do you mean by RISC processor? Explain in brief.

(b)    Compare fuli custom and semi custom design.

(c)    What is GCA (Gradual Channel approximation)7 Derive current vo!tage equations of MOS transistor.

Q.4    (a) Explain tłie operation of two-input depletion load NOR gate.

(b)    Explain operation of CMOS iiwerter.

(c)    Explain resistive load inverter and derive its critical voltage points

OR

Q.4    (a) Explain eon troi labi lity and observabi lity.

(b)    Explain behavior of bistable elements in brief..

(c)    Explain operation of CMOS transmission gates (TGs) in detail.

Q.5    (a) What is UML (unified modeling language). Explain in brief.

(b)    Explain clock generation and distribution techniques.

(c)    What is the need for voltage bootstrapping? Explain dynamie voltage bootstrapping Circuit with necessary mathematical analysis.

OR

Q.5    (a) What is significance of threshold voltage in MOS transistor? Write

expression of threshold voltage.

(b)    Explain Built in self test (BIST) method in detail.

(c)    Explain NAND gate using CMOS realization. pass transistor and Complementary pass transistor realization.

*************

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