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Pentium(r) III Processor Architectural Błock Diagram

System Bus

1

Fetch/Decode

Control

Micro Codę ROM! Micro Instruction Seciuencer

Instruction Cache 16 Kbyte. 4-way 32 entry TLB

3 x parallel Instruction Dec

Dynamie Branch Predictor: 512 entries

Static Branch Predictor

Bus

Interface

Unit

133 MHz 64-bit 1 GB/s

L2

Cache

L2

Cache

Control

Unit

Integer/FP Register Rename & Allocator

Reservation Station (20 Entries)

AGU

Architectural Register File

Storę Data Unit

Storę

Address

Address

Unit

Shift

MMX

MMX

Memory Order Buffer 12 entry storę. 16 entry load

T

Data Cache 16 KByte. 4-way

72 entry TLB

Reorder Buffer

(40 entries)