RX
A10 LOCAL A9
OSCILLATOR
U10 / TX VC1 VC4
1
GSM 0
Osc.
800MHz
D8
discrete
DCS 0 PLL
1
circuty
Q203
U200
VC4
C8
MAGIC
CR249
RF_V2
DCS RVCO RF_V1
2
J100
1
D101
1 2,3,5,
Mech. Ant Switch
( SCLK_OUT ) BCLKR
FL472
400 MHz
6,20 10
VC1
11 F7
5
1
B C
1805-1880MHz 5 PRE_IN
RX ( SDFS ) BFSR
A7 RXI
STEP
RX
DCS 4 to WhiteCap
G9
9 2 Q490 DEMODULATION
U432
FL490
ATT.
SPI
RXQ
FRONTEND IC 3 ( SDRX ) BDR
GSM
Filter C
1 G8
7
925-960MHz
SW_VCC
C7
VC2
7
2 5
16 24
2
C6
FL480
3
4 G1
2,75V
RF_V2 D2 F1
GSM RX_EN DCS_SEL G2
VRef
VC1
B+ H1
5 J7
S1
PHASE
B+
DET
2
S2
6 1 Divider
D1
2,75V RF_V1 G1
H2
200KHz CR248
J9
Q201
13MHz
F9
RVCO
C8,H7;B3
MAGIC_13MHz
RX VCO MID CHANNELS J6
to WhiteCap
MUX
GSM: CH 62 -- 1347,4 MHz CLK_SELCT
G6 from WhiteCap
C1
EGSM: CH 37 -- 1342,4Mhz SF_OUT
Startup
DCS: CH 700 -- 1442,8MHz
6 Ref.
2
Inverter 1 /2
Q313 A1
RX VCO FRQ. RANGE TX_EN 1
5 PHASE Prog. F2
TX FRQ. RANGE EGSM: 1325 - 1360Mhz RVCO
4 B1
Q313
Divider
REF. OSC.
DET
EGSM: 880-915Mhz
DCS: 1405 - 1480MHz
3 200KHz
DCS: 1710-1785MHz 26 MHz
PA_B+ AFC
5 Divider 26MHz Y200
REF.
4 A3
11 3
Q312
Iso.
RX_LO_OUT PLL
U253
6 Switch TX LOOP
U506 PA 6,8 12
Q312 V1_SW
6
1 FILTER
2 C2
GSM_PA_OUT 4 GSM_TX_RF_OUT ( CE ) MQSPI_CS1
10
14
G5
SPI
( SPI_CLK ) MOSPI_CLK1
DCS_PA_OUT DCS_TX_RF_OUT
12 2 LOGIC
16 1 GSM_TX_VCO C4 H4
GP02 INTER
DCS_TX_VCO ( SPI_DATA ) DX1
CONTROL
RX / TX13
J3
TX VCO FRQ. RANGE DCS_SEL FACE
2
PAC_275 14
VCO
EGSM: 880-915Mhz TX_EN
4
DCS: 1710-1785MHz
from WhiteCap
U501
3,14 4 5
DCS_SEL
TX VCO MID CHANNELS
1
RF DET PAC
GSM: CH 62 -- 902,4MHz
RF_IN
EGSM: CH 37 -- 897,4Mhz
BUFFER - 6 VCTRL
DCS: CH 700 -- 1747,8MHz
AMP
( SDTX ) BDX
+ - + Bias Switch
(Gain 1or 3)
TXI TX J2
INTEGR.
RF_V2
COMP.
MODULATION
Q506 ( TX_CLK ) BCLKX
TXQ SPI
+ - G7
SAT.
PAC_275
DET.
DM_CS
Q505
9 8 10 11 7
Mute Switch
if DM_CS is low
Logic 1 at low power VCTRL is pulled to GND
RX_ACQ
AOC_DRIVE AOC_DRIVE B6
Logig 0 at high power
H8
DM_CS
LOGIC
SAT_DETECT SAT_DETECT B4
J4 from WhiteCap
PA
TX_KEY
A5
CONTROL
DETECT_SW DETECT_SW CONTROL
H5
GPRS_TX
C5
TX_KEY_OUT TX_KEY_OUT
DCS_SEL
DCS_SEL
RX SIGNAL PATH REFERENCE CLOCK
GSM_TX_VCO
RVCO
DCS_TX_VCO
RF_V2
GSM SERVICE SUPPORT GROUP 12.07.01 Orderable Part
PAC_275 TX SIGNAL PATH
GSM / DCS SELECT CIRCUIT
TX_EN
VC1
LEVEL 3 RF Block Diagram Rev. 1.0
VC4 DM_CS
MAIN VCO SIGNAL PATH Non - Orderable Part
T192 ( Barracuda )
TUNING VOLTAGES
Ralf Lorenzen, Michael Hansen, Ray Collins Page1
SWITCH
REG.
SWITCH
SUPER
FILTER
T192 (Barracuda)
VDDS
C4, H4, K5
V2
WHITE_CAP
VCC_MEMIF
KBR0-KBR2 H2, H1, H3 C14, F10, K13, P13
( Keyboard )
VDD
A9,A10, C5, M8, M11
KBC0-KBC3 J5, J3, J2 U700 V3
G12 VCCA
KEYPAD
( CE ) MQSPI_CS1
BKLT_EN K3 DISPLAY
N8 J902
SPI
A11
DP_EN_L INTERFACE ( SPI_CLK ) MOSPI_CLK1
K7 ( MAGIC SPI )
Display Con.
INTERFACE ( SPI_DATA ) DX1
RSTO E9
M7 D7 - D0
SIM
E7
CLKO
15-22
INTER
SIM_TX F3 M
DATA BUS
FACE
SIM_RX B5 E
A0
M
23
M3
EXTB+_DET ADDRESS BUS
UART O
N3
HEAD_INT R
L2 Y 14,26
BATT_THERM V2
CLK_SELECT A1
SR_VCC RESET 24
I
TX_EN C1 CPU D6, E1 V2
CTM
A4, E1, F5
CE2 4
R_W
N
DM_CS
E2 B2
C9
MODULE U702
T RESET DP_EN_L 25
CE3
TX_KEY E1 U701
B4
A1
E10
E SRAM
RX_EN E3 GND 1-6,13
R_W
EPROM
R
B11 G5
RX_ACQ E4
15
-5V
F
B3EEPROM
RESET E8
CE0
A D7
D9
( SDTX ) BDX
C
CE1
B6 KBR0 - KBR2
B9 F8
KEYBOARD
E
( TX_CLK ) BCLKX ( WhiteCap )
B3
SERIAL KBC0 - KBC3
( SCLK_OUT ) BCLKR CTM ( GCAP2 )
INTER
F1 ON_2
from / to MAGIC DSP
DEEP SLEEP
B4
( SDFS ) BFSR FACE
CIRCUIT
STBY_DL
L7
D4 ENABLE
( SDRX ) BDR
( GCAP2 )
ALRT_VCC
BACKLIGHT
A3
P6
CHARGE TRKL_SET
DSC_EN
DSC
K2
TP4
(Magic)
V1
Q913
V1_SW
( White Cap )
BKLT_EN Q902
SPI
TIMER
INTERFACE ( GCAP2 )
ALRT_VCC VIB 1 VIB 2
B7 P4 H10
BATTERY
VIB_EN Q901
CONN. V2
CHARGER M901
D902
EXT_B+
Q900 R923 B+ 3,4
B+
TP2 B+
V2
BATT_THERM_AD ( GCAP2 )
U903
CHARGER JACK
ISENSE
2,5
GND
8
1
J903
Q903 EXTB+_DET
7
2
F5 COVIC
TRKL_SET 3 6
PWR_ON
1,6
BATT_ID
EXT_B+ A7 B7
C7
CLK
F6 3 J902 4 5
SPI ENABLE
REAL TIME RESET
LEVEL
SIM
INTERFACE
J7
2
CLOCK
Con.
SHIFT SIM_I/O
J8
6
1,5 VSIM1
4
MAN_TEST_AD
R931 A1 U900
K7 RSTO
Mode Full Rate High Trickel Low Trikel Off
CLKO
G6 ( White Cap )
BATT_THERM
Q914
SENSE Current 300mA 100mA 40mA <1mA
BATT_ID A3 SIM_TX
K10
G_CAP2
B3 CNTL. H8 SIM_RX Low
BATT_THERM_AD TRKL_SET High Low High
GND
V2 ENABLE
High Low Low High
TP1
D10
PWR_ON
C4
C8
Logic Control
RESET ON2
ON2
G4
TP5
G5
STBY_DL
VREF G9
VREF 2.775V for Magic
REG.
V3 B5
UPLINK V3 1,8V, for WhiteCap
D2
REG.
TP3
E1
C3
SR_VCC 2.775V, for SRAM
DOWNLINK
TP6
J5
V2
J900 V2 2.775V, for WhiteCap logic outputs, RAM, FLASH, EEPROM
REG.
MIC J2
A6
V1
MIC V1
5.0V, for DSC Bus, Negative Voltage Regulator
REG.
VSIM C6
Interface
VSIM1 3.0 or 5.0V, for SIM Card Circuit
REG.
AUX_MIC A10
Audio
HEADSET H3
Codec
VBOOST1
F7
CON.
REG.
H9
H6 H7 K9 J9 K5 E10
B10
J504 1
3
RX SIGNAL PATH
4
TX SIGNAL PATH
2
SPKR
MAIN VCO SIGNAL PATH
GSM SERVICE SUPPORT GROUP 12.07.01
Internal GCap use only (VSIM1, LS_V1)
3 D900
1,2,5,6
TUNING VOLTAGES
4
LEVEL 3 AL Block Diagram Rev. 1.0
Q904 L901
V_BOOST1
REFERENCE CLOCK
ALRT
C956
LS900
ALRT_VCC T192 ( Barracuda )
Orderable Part
IRQ_2
B+
Ralf Lorenzen, Michael Hansen, Ray Collins Page2
Non - Orderable Part
ALRT_VCC
13 MHz
R941
MAGIC_13MHz
32.768 KHz
GCLK
RT900
GCAP SPI
Y900
GCAP_CLK
AUDIO SPI
R944
R605
PA_DRV
SPR+
SPR-
ALRTOUT
T192 (Barracuda)