RX MID CHANNELS
850: CH190 -- 881,6
GSM: CH 62 -- 947,4 MHz
Internal
EGSM: CH 37 -- 942,4Mhz
Antenna
DCS: CH 700 -- 1842,8MHz input output
VCO_REG
M100
PCS: CH 661 -- 1960MHz Pin 8 Pin 9 Ant Port Conn
Pin 13
1 0 0 TX_LB
18,31
DCS/PCS OUT 1 1 0 TX_HB
TX_HB
J100 Mechanical
2 4 25
1 0 0 0 PCS
FL109 2 3
Antenna Switch
6
0 0 1 DCS
11, 20,
B+
21, 30,
0 1 GSM850
0
14
4 TX_LB
2 26
0 1 1 EGSM
1 2 3
FL108 Power and
Antenna
GSM850/
Control
U200
GSM900 OUT
PA + Antenna Switch
16 15 9 13 8 17
4 3 2 1 10
850 MHz
NEPTUNE LTE2
H1 IO_REG (VCC + 2.775V)
900 MHz
U800
PA Power Control selection via VRAMP, TX_HB and TX_LB Power
(VCC + 2.775V)
C5,A11, ...... PERIPH_REG
DSP Peripherals
(VCC + 1,575V)
1. IPC: Input Power Control mode - for EDGE mode E2 REF_REG
accelerator, encryption
(VCC + 1,875V)
1800 MHz (PA gain is fixed and PA input power varies) L19, V2, .... VBUCK
Timer, Interupts
(from Atlas )
SIM_REG
2.BCM: Bias Control mode - for GMSK mode
K2
(Data In /OUT)
SIM DIO
(PA gain varies according to power step and fixed input PA power)
1900 MHZ
K3
(Reset )
SIM_RST
U6 L1 Timer DSP
SIM
DSP J4
(from / to J24_DB)
Memory (Clock )
UltraLite Interface SIM_CLK
L1
104 MHz
SIM_PD
R1
(from Atlas )
(to Atlas)
M1 VSIM_EN
D0-15
DATA BUS
Shared Memory
A1-24
1Mbit RAM
ADDRESS BUS
Transceiver
U100
FL100
A1
Quadband Saw Filter A4 B3 C3 C2 A2 B2 E2 B9
W19 CS0B D3
U701
N10
and Matching
MCU V17
External CS1B G8
14 K12 MCU
PA Control GPIO G1 SYSCLK_EN Memory
1 W10 T18 CS2B D6
ARM7
(from Atlas) Memory
LNA
High Band 15 L12
52 MHz
GPIO G17 EB1B F3
1900MHz U9
Interface
MEMORY
K16 EB0B C2
12 G12
3
(RX Data) T8
G2 DRI
LNA J19 F4 RESET OUT (from Neptune)
R_WB
High Band 13 H12 F5,D5
LPF
1800MHz Digital Radio T16
OEB
D1 J2,H1,H8
MS (TX/RX Enable)
(from Atlas)
10 D12 DC E4... VBUCK
T19 BURSTCLK C6
26 MHz
A4
4 Correct Receiver Clock Generator
LBAB E5
L16
E3 (TX Data) Oscillator
Low Band LNA MDI
11 E12
N18 ECBB G7
900MHz
16 MB SRam
8 A12 DBG_DATA (SPI readback) LCD_RD
G3 D14
RX CP 64 MB Flash
6 (only used in Engineering debug mode
LCD_RS
Low Band LNA 4 P2
÷
9 B12
- not for Service)
LCD_CS
850MHz 90° MQSPI N3
M4 LCD_CLK_DATA6
RX VCO Display
(LCD Control to J1300 )
P1 LCD_SDATA_DATA7
L8
÷2 F3
SYSCLK LCD DATA (0 - 5)
L3...
90°
J1 (to U400)
GA_SPI_CS
BT_CLK D18
L10 J3 BT_CLK_EN
1
TX VCO
TX CP K5 2, 4
(Bias output for THERM signal)
Y100 U10 TOUT12
÷2
3
K4 26MHz
(EL Backlight Enable to U1370)
N9 EL_EN
(Data In /OUT)
GPIO
D2 RF_DATA (Trans Flash Enable to U970 )
PA12
U8 W8
Phase Modulation
(Clock ) (U100 Control Bus)
F1
RF_CLK
V7 SPI (to Atlas U900)
TX_EN_BM
(Chip select) V8
÷2
E1
RF_CS W9
On A14 (to U901)
PE12
Off
C10
VCO_REG
J5, J8
VM_REG
One BaseBand UART2 Hall Effect
ADC
LPF LPF
UART / USB
Transmit H2 VBUCK Timer
Keypad Serial Audio
Wire Universal
(VCC s from Atlas)
Voltage B4 MQSPI
RF_REG Interface Port Interface
Modulator
BT
Amplitude Modulation Interface Interface Bus Asynchron.
1
C1 (Flip Open/ Close
Reg. IO_REG
HS INT
(rx) (tx) C14 U1220
Rx /Tx
Detect)
C5
REF1V2
A17 C15 D15 A15 F3.... V12 W12 V13 E3 U11 A12 B13 N13 D16 B15
6
G3..... W13 D13 N17 V16 D19 T7
B16 C16 A16 T11 T10 W5 W11 B12
V11 B14 G8 U13
PERIPH_REG
Neptune /Atlas Neptune /Atlas (from/ to U301 BT, J1300
(from/ to Neptune
USB/ RS232 Communication Serial Audio for Ringtone Neptune - BT - Neptune
2
Communication and Voice Audio) Communication and Wakeup)
(To J1300)
U806
Revision Overview
Level
Rev. 1.0: Initial Block Diagram
Shift
4
Key-Matrix
0-9,*,#
Navigation,
Smart,
Volume
Servive, Engineering & Optimization 2007.2.27
LEVEL 3 AL Block Diagram Rev. 1.0
W510
W510
Page 1of 3
(PA Power Control)
(Transmitt Enable)
TX_EN
VDETECT
LB_HB
US_EURO
TX_ANT_SW_EN
IPC_BCM
VRAMP
TX_START
RESETB
(Transmitt Enable)
RX / TX
In / Out - Put controler
Synthesizer
Clock
Serial
RX / TX
Interface
(clock)
(framesync)
OWB
CLK 13 MHz
(from U600 via J1300)
BB_SPI_MISO
BB_SPI_MOSI
AUL_CS
AUL_INT
GA_INT
STANDBY_1_5V
BB_SPI_CLK
BLUE_RTSB
BLUE_WAKEB
BLUE_TX
BLUE_CTSB
KBC0-1
BLUE_HOST_WAKEB
KBR0-7
USB_VPIN
USB_XRXD
USB_VPOUT
USB_VMIN
USB_TXENB
USB_VMOUT
BLUE_RX
BB_SAP_RX
TOUT9
BB_SAP_TX
BB_SAP_FS
BB_SAP_CLK
(13 MHz)
One Wire data from Battery (from M1220)
PC13
(Watchdog)
PC0
RESETB
RESET OUT
CLK 32KHZ
STANDBY
(to Atlas )
(to J1300)
(from Atlas)
(to U701)
(to Atlas)
WDOG
(from Atlas)
Main Connector
U1370
Main CONNECTOR
SIM
EL LAMP Driver
Connector J1300
8 TP12
EL_EN 3
1 2
GND MSIM_PWR GND
49 50 GND
(from FL1360 SDCLK_OUT) 3 4
MSIM_SDCLK
VBOOST 10 R1370 SIM_RST (from Neptune)
(from U600) (from D601)
SDCLK 47 48 CHRGLED
5
(from/to Neptune) SIM_DIO 6
SIM_CLK (from Neptune)
SD0
45
(SD Card Data 46 GND
TP13 7 8
(from FL1360 SDCMD_OUT) MSIM_SDCMD MSIM_SD0 (from FL1360 SD0_OUT)
from/ to U600 SD2 (SD Card Command to/from U600)
44 SDCMD
43
via FL1360)
SD3 41 42 SD1
J1350
VBUS
GND 39 40
4 5
LCD_DATA0
CAM_REG 37 38 R1300
3
6
VBUCK 35 36 R1300 LCD_DATA1
(from Atlas) (LCD Data from Neptune)
2
7
PERIPH_REG 33 34 LCD_DATA2
R1300
1
8
IO_REG
31 32
R1300 LCD_DATA3
(from U1370 for ATI core supply)
GRAPH_REG
29 30 (from Atlas)
LEDR1
4 5
(from Atlas)
GSDRAM_REG R1301 LCD_DATA4
27 28
TF Card
3
6
Connector BB_SAP_RX 25 26 R1301 LCD_DATA5
2
7 (LCD Data from Neptune)
23 24
(Control Bus for ATI BB_SAP_TX R1301 LCD_CLK_DATA6
1 SD2_OUT
1
from/ to Neptune) 8
BB_SAP_FS 21 22
R1301 LCD_SDATA_DATA7
2 SD3_OUT
BB_SAP_CLK 19 20
3 GND
SDCMD_OUT
12 SD2
4 GND 17 18 LCD_CS
J1360 TF_PWR(from U970) 11 1 SD3
2
5
SDCLK_OUT (from Atlas) VBOOST 15 16 LCD_RS
10 3
SDCMD
(from U600)
6
GND (LCD Control from Neptune)
9 4 13 14
(on PCB) SDCLK DISP_LED4 LCD_RD
7 SD0_OUT 8 5
Strip Line SD0 11 12
DISP_LED3 GA_SPI_CS
Bluetooth 8 7 6
(from Atlas)
SD1_OUT SD1
Antenna DISP_LED2 9 10
PCO
DISP_LED1 7 8
GND
to Neptune)
(interupt from U600 GA_INT HAND_SPKR-
5 6
(from Atlas)
Bluetooth CLK_32KHZ_2_7V 3 4 HAND_SPKR+
PERIPH_REG B3...... g1- g4, 1, 2
(from Atlas) GND
B+ H6
BLUE_RX E5 LDO for TF Card
2
A1
C1
BLUE_TX E4
25
TF_PWR PERIPH_REG
(from/ to Neptune
BLUE_CTSB E8 B2
U970C3 B+ (from Atlas)
(from/ to U400 BT, Serial Audio for Ringtone GND
SYSCLK_EN
BLUE_RTSB E7
Neptune - BT - Neptune and Voice Audio)
A3
Communication and Wakeup)
5
4
H1
C8 U400
BLUE_WAKEB
H2
BLUE_HOST_WAKEB C6
BB_SAP_RX
Charger and Power-
C4 C7 BATT CONN.
STANDBY
BB_SAP_FS (framesync) Neptune Atlas
source Control
BT_RESET_B E3 Neptune /Atlas
A7 USB/ RS232
BB_SAP_CLK(clock) Communication M1220
Communication
(to U100)
BT_CLK_EN D7
B6
BB_SAP_TX
(from U100) E2 Charger
BT_CLK
3 2 4 1
C5
(from Atlas) F6
CLK_32KHZ
(from Acesory Connector)
(from U800, shutdown BT) E3
TOUT9 (EXT Power)
VBUS
(One Wire Bus
to Neptune)
OWB GND
(to Neptune)
T14 SIM_PD
(from J1300)
L10 CHRGLED
P1261
13 Bit SAP (tx) (rx) C15 CHRGRAW
(VBUS Sense)
PRI SPI
2
ALERT- V10
USB/RS232 CNTL.
PCB ON AD
P13
(Bias Voltage from
Alert CODEC TOUT12
THERM THERM
ALERT
NeptuneAtlas LOGIC
D14
Amplifier 16 BIT (Battery Sense) Neptune)
1 ALERT+ U8 BATT+
Pads (communication) Neptune Atlas LOGIC CONV.
STEREO
F13
Communication BATTISNS
D/A
(Batt Current)
U14
Handset
HAND_SPKR- T6
(to J1300)
Amplifier (Charger Current + )
E15 CHRGISNSP
HAND_SPKR+ R7
Q905 (M1) S
Internal
P9
4 MIC_BIAS1 G
Color definition only for this section !
Microphone
CHARGE
MIC 1 MIC_INM
T9 (Current Control) Main Charge Path
B16 CHRGCTRL
Supply R910 R911
CONTR.
B+ support without Ext Charger
D
MK1200
Amplifier B+ support with Ext Charger
S
Q906 (M2)
3
G
1
Headset Q904 (M3)
2
(Main Source
NC B12
BATTFET
B+
Amplifier
Logic for Atlas)
BPFET
B14
Stereo Battery to BPLUS
Det. Switch D
G
C6 DISP_LED1
Mini USB Headset Q903 (M4)
NC LED
B6 DISP_LED2
Det.
CNTL.
D6 DISP_LED3
(to J1300) S
(to Charging Circuit)
1 VBUS
F8 DISP_LED4 VBUS to BP
Switch
D9 LEDR1 (from Mini USB Connector)
(from Atlas) VBOOST B4 VBUS 5V
U900
D903 (EXT Power)
(PPD device support) Pass FET VBUS
VBUS D2 D12 (from J1230)
RTC_BATT
ATLAS UL
V17
USB 1
(Accessory Detection signal)
4 UID H8
3 4 EMU Y900 32.768KHz
F3
D-
2
2 1 V16 2
FL1390 Interface
E3
D+
3
R16 CLK_32KHZ (to Neptune and U400 BT)
(to J1300)
P16 CLK_32KHZ_2_7V
5 TIMER
(from Neptune)
Headset detect circuit CLK_13MHZ
V12
(from Neptune)
WDOG
G1-G4 K10
U901
(from Neptune, Tx Mode indication for Atlas)
TX_EN_BM
U15
(Shield) (Bias from Atlas)
C2 B1
R985
PERIPH_REG
(to U100)
SYSCLK_EN
P14
A1
(100K Headset
(from U800)
STANDBY
F12
detect Resistor)
(to Neptune, U200 & U970)
E12 RESETB
PE12
(Headset detect Enable from Neptune) Revision Overview
4
Rev. 1.0: Initial Block Diagram
input output
A1 B1 C2 3
1
L H H
L L L
H X Z
2
M1221
1
2 Servive, Engineering & Optimization 2007.2.27
LEVEL 3 AL Block Diagram Rev. 1.0
W510
W510
Page 2of 3
FL1360
BT_ANT
FL401
(Bias)
PERIPH REG
AUL CS
USB_VPIN
USB_VPOUT
USB_TXENB
BB_SAP_TX
BB_SAP_FS
BB_SAP_RX
BB_SAP_CLK
BATT+
R940
R4
R5
B3
E4
USB_VMOUT
C4
USB_XRXD
F4
P4
R3
B2
F14
ON1B
T17
BB_SPI_CLK
T18
BB_SPI_MOSI
N14
AUL_INT
U18
U16
BB_SPI_MISO
B1,..
USB_VMIN
R941
J1390
VR1391
VR1390
VR1392
REG
REG
VCO
REG
REG
VSIM
Switcher
Switcher
IO REG
AUDIO
B+ Sense
PERIPH
IO REG
GRAPH
RF REG
RF REG
to Vibrator
DIG REG
REF REG
REF REG
Buck 350mA
CAMERA
VIB REG
Boost 300mA
P2
Motor
N5
K16
H3
H4
K17,...
U6
H2,...
F16
B4,....
R17
K11
J16,J4,J15........
Q910
VCO_DRV
V2
( 1,3V )
VIB_REG
BUCKOUT
F17
B+
VSIM_EN
( 1,2V )
REF1V2
( 2,775V )
PERIPH_ REG
(2,775V )
VM_REG
( 2,775V )
RF_REG
( 2,775 )
IO_REG
( 1,8/ 3V )
SIM_REG
( 2,775V )
AUD_ REG
( 1,575V )
REF_REG
L16
( 1,275 )
GRAFX_REG
( 5,5V )
VBOOST
( 1,875V )
VBUCK
( 1,8V )
GSDRAM_REG
P18
(from U800)
(to U250)
(to U250)
( 2,775V )
VCO_REG
(to U250)
(to Neptune)
(to AL + RF))
(to AL + RF))
(to AL + RF))
J3500, U1501)
(only used in Atlas)
(to J2, J1000, D1000
(to Neptune amd J27)
(to J2, J1000, J2000)
(Main Source- from Q904)
(to J2, J1000, Q2020)
( 2,775 )
CAM_REG
(to U50,U250)
Hinge Flex Connector
ATI
VBUS VBOOST
Flip CONNECTOR U600
1 2
J601
D601
GND R5
(for Camera)
Pwr N8 VBUCK
GND 3 4
50 49 GND GND W5
(for CPU, GPIO)
Mgt F12 PERIPH_REG
(from U600) (from D601) LEDRED
SDCLK 47 CHRGLED
48 V7
CAM_SDA
H10 GRAPH_REG (for ATI Core)
SD0
(SD Card Data 45 GND
46
CAM_SCL W7
Camera V19 IO_REG
from/ to U600 SD2 (SD Card Command from U600)
SDCMD
44 43
via FL1360) CAM_VSYNC
V8
SD3 SD1
42 41
CAM_HSYNC
GND VBUS W8
40 39
LCD_DATA0 H19 LCD_DATA0
CAM_REG
38 37
CAM_CLK_IN W6
H15
VBUCK LCD_DATA1 LCD_DATA1
36 35
(from Atlas) (LCD Data from Neptune)
CAM_CLK_OUT W9
PERIPH_REG LCD_DATA2
34 33 LCD_DATA2 H13
R6
IO_REG CAM_D0
32 31 CPU J19 LCD_DATA3
LCD_DATA3
(from U1370 for ATI core supply)
GRAPH_REG T6
(from Atlas) CAM_D1
30 29 LEDRE0
J15 LCD_DATA4
(from Atlas)
GSDRAM_REG LCD_DATA4
28 27 T7
CAM_D2
J16 LCD_DATA5
LCD_DATA5
BB_SAP_RX
26 25
V6
CAM_D3
(LCD Data from Neptune) LCD_CLK_DATA6
K16
LCD_CLK_DATA6
(Control Bus for ATI BB_SAP_TX 24 23
R7
CAM_D4
K15
from/ to Neptune) LCD_SDATA_DATA7
BB_SAP_FS 22 21 LCD_SDATA_DATA7
CAM_D5 T8
BB_SAP_CLK U19 ATI_32KHZ
20 19 GND
GND CAM_D6 R8
LCD_CS
GND 18 17 H16
PCO (Reset)
CAM_D7
R9
(from Atlas) VBOOST
16 15 LCD_RS
P16
IO_REG
(LCD Control from Neptune)
DISP_LED4 14 13 LCD_RD
P15
LCD_RS
DISP_LED3 12 11 GA_SPI_CS
LCDC_CS B2
(from Atlas) M19 LCD_CS
DISP_LED2
10 9
PCO
LCDC_SDO
C1 P19 GA_SPI_CS
DISP_LED1
8 7
GND
5 LCDC_SCLK B3
to Neptune) N19 LCD_RD
(interupt from U600 GA_INT HAND_SPKR- 4 TP_HS
6 5
(from Atlas)
FL600 CLI_RESET B1
1 E14 GA_INT
ATI_32KHZ HAND_SPKR+
4 3 TP_HS+
8
CLI_CS
g1- g4, 1, 2 D5
GND
LCDC_RESETB D1
J4 LCDC_RED0
GPIO
CLI_CLK D4
M2 LCDC_RED1
CLI_RS E5
K4 LCDC_RED2
CLI_DATA E2
H4 LCDC_RED3
GND
LCDC_SD
F1
LCDC_RED4
N2
GND
G2
J5 LCDC_RED5
LCDC_SDI
G1
L4
LCDC_GREEN0
LCD
GND H2
L1 LCDC_GREEN1
CAM_PWRDWN H1
K5 LCDC_GREEN2
CLI Display Connector CAM_RESET L2
L5 LCDC_GREEN3
BB_SAP_CLK W2
M1 LCDC_GREEN4
J604
BB_SAP_FS V1
M5 LCDC_GREEN5
8 CLI_CS BB_SAP_TX
V2
M4 LCDC_BLUE0
7 CLI_RESET BB_SAP_RX V4
N1 LCDC_BLUE1
(from U600)
6
CLI_RS
N5 LCDC_BLUE2
5 CLI_CLK
SD0 D19
P2 LCDC_BLUE3
4
CLI_DATA
SD1 D15
N4 LCDC_BLUE4
3
VBUCK SD
SD2
C19 LCDC_BLUE5
P4
2 PERIPH_REG
SD3 B19 LCDC_DCLK
T1
G1- G2,
GND E19
SDCLK LCDC_OE
R1
1, 9
IO_REG B18 LCDC_LS
R2
SDCMD D14 P1 LCDC_GS
Main Display Connector
Camera Connector
J602
J600
24
CAM_CLK_IN 23 CAM_SCL
22
LCDC_SDO 40 GND GND 21 CAM_SDA
39
20
LCDC_RESETB 38 CAM_CLK_OUT 19 CAM_D0
37 GND
17 CAM_D1
36 GND 18
35
LCDC_SCLK LCDC_BLUE5
16
34 CAM_D3 15 CAM_D2
33
LCDC_CS LCDC_BLUE4
14
32 CAM_D5 13 CAM_D4
LCDC_SD 31 LCDC_BLUE3
12
30 LCDC_BLUE2 CAM_D6
LCDC_SDI 29 CAM_D7 11
10
28
LCDC_DCLK 27 LCDC_BLUE1 CAM_VSYNC 9 CAM_HSYNC
8
26 7 GND
GND 25 LCDC_BLUE0 GND
6
24
LCDC_LS 23 LCDC_GREEN0 GSDRAM_REG 5 CAM_REG
4
22 CAM_PWRDWN 3
LCDC_GS 21 LCDC_GREEN1 VBUCK
20
LCDC_OE 19 LCDC_GREEN2 2 1 CAM_RESET
GND
18
VBUCK 17 LCDC_GREEN3
G1- G4
GND
GND 16
15 LCDC_GREEN4
PERIPH_REG 14 LCDC_GREEN5
13
12
GND 11
LCDC_RED0
10
9
DISP_LED4 LCDC_RED1
8
DISP_LED3 7 LCDC_RED2
6
DISP_LED2 5 LCDC_RED3
DISP_LED1 4
3 LCDC_RED4
Revision Overview
VBOOST 2 1 LCDC_RED5
Rev. 1.0: Initial Block Diagram
G1- G4
GND
Servive, Engineering & Optimization 2007.2.27
LEVEL 3 AL Block Diagram Rev. 1.0
W510
W510
Page 3of 3
RED
GRN
VR601
VR602