RX MID CHANNELS
850: CH190 -- 881,6
GSM: CH 62 -- 947,4 MHz
Internal
EGSM: CH 37 -- 942,4Mhz
Antenna
DCS: CH 700 -- 1842,8MHz
VCO_REG
M1
PCS: CH 661 -- 1960MHz
18,31
ANT_DET_B (indicates mechanical Antenna connection to U800)
DCS/PCS OUT
TX_HB 25
J7506 Mechanical
4 2
FL82 1 2 3
Antenna Switch
6
11,14....
BP
2 TX_LB 26 BP
4
1 2 3
FL54 Power and
Antenna
GSM850/ 5,6
Control
U50
GSM900 OUT
2
U807
PA + Antenna Switch
IO_REG
16 15 9 13 8 17
4 3 2 1 10
Switch
3
850 MHz
REG_BYP_CORE
M18
NEPTUNE LTE2
H1 IO_REG (VCC + 2.775V)
900 MHz
U800
PA Power Control selection via VRAMP, TX_HB and TX_LB
(VCC + 2.775V)
A11, U16, ..... PERIPH_IO_REG
DSP Peripherals Power
(VCC + 1,575V)
1. IPC: Input Power Control mode - for EDGE mode E2 REF_REG
accelerator, encryption
(VCC + 1,875V)
1800 MHz (PA gain is fixed and PA input power varies) V5, R16, .... VBUCK
Timer, Interupts
(from Atlas )
VSIM
2.BCM: Bias Control mode - for GMSK mode
K2
(Data In /OUT)
SIM DIO
(PA gain varies according to power step and fixed input PA power)
1900 MHZ
K3
SIM RST (Reset )
U6 L1 Timer DSP
SIM
DSP J4
(from / to J24_DB)
Memory
UltraLite Interface SIM CLK (Clock )
L1
104 MHz
SIM_PD
R1
(from Atlas )
(to Atlas)
M1 VSIM_EN
D0-15
DATA BUS
Shared Memory
A0-23
1Mbit RAM
ADDRESS BUS
Synthesizer
U250
FL100
A1
Quard Saw Filter A4 B3 C3 C2 A2 B2 E2 B9
W18 CS0B K1
U700
N10
and Matching
MCU V17
External CS1B G8
14 K12 MCU
PA Control GPIO G1 STANDBYB Memory
1 W10 T18 CS2B D6
ARM7
Memory
LNA
High Band 15 L12
52 MHz
GPIO G17 EB1B F3
1900MHz U9
Interface
FLASH
K16 EB0B C2
12 G12
3
T8
G2 DRI (Data TX)
LNA J19 F4 RESET OUT (from Neptune)
R_WB
High Band 13 H12 F5,D5
LPF
1800MHz Digital Radio T16
OEB
D1 J2,H1,H8
MS (TX/RX Enable)
(from Atlas)
10 D12 DC E4... VBUCK
T19 BURSTCLK C6
26 MHz
A4
4 Correct Receiver Clock Generator
LBAB E5
L16
E3 (Data RX) Oscillator
Low Band LNA MDI
11 E12
N18 ECBB G7
900MHz
16 MB SRam
8 A12 MISOB (readback) LCD_OE
G3 D14
RX CP 64 MB Flash
6 (only used in Engineering debug mode
LCD_RS
P2
Low Band LNA ÷4
9 B12
- not for Service)
LCD_CS
850MHz 90° MQSPI N3
M4 LCD_CLK_DATA6
RX VCO Display
(LCD Control to J2 )
P1 LCD_SDATA_DATA7
L8 ÷2 F3
MCLK LCD DATA (0 - 5)
L3...
90°
J1
LCD_WEB
BT_CLK D18
L10 J3 BT_CLK_EN
(indicates mechanical Antenna connection to U800)
ANT_DET_B
U12
1
TX VCO
TX CP K4 2
(Bias output for THERM signal)
Y201 U10 TOUT12
÷2
3
K5 26MHz
(EL Backlight Enable to U1501)
N9 EL_EN
(Data In /OUT)
GPIO
D2 RF_DATA (Trans Flash Enable to J27 )
TF_ENABLE
U8 W8
Phase Modulation
(Clock ) (U250 Control Bus)
F1
RF_CLK
V7 SPI (to Atlas U900)
TX_EN_SW
(Chip select) V8
÷2
E1
RF_CS W9
(to Atlas U950 )
EMU_HDST_DET
On A12
Off
C10
VCO_REG
J5, J8
VM_REG
One BaseBand UART2 Hall Effect
ADC
LPF LPF
UART / USB
Transmit H2 VBUCK Timer
Keypad Serial Audio Inverter
Wire Universal
(VCC s from Atlas)
Voltage B4 MQSPI
RF_REG Interface Port Interface
Modulator
BT
Amplitude Modulation Interface Interface Bus Asynchron. 2
4 1
C1 (Flip Open/ Close
Reg. IO_REG
HS INT
(rx) (tx) C14 U1401 U1600
Rx /Tx
Detect)
C5
REF_1p2
A17 C15 D15 F3.... V12 W12 V13 E3 U11 A12 B13 N13 D16 B15
5 6
F2.... W13 D13 N17 V16 D19 T7
B16 C16 A16 T11 T10 W5 W11 B12
V11 B14 G8 U13
PERIPH_IO_REG
Neptune Atlas Neptune Atlas (from/ to U301 BT, J1300
(from/ to Neptune
USB/ RS232 Communication Serial Audio for Ringtone Neptune - BT - Neptune
2
Communication and Voice Audio) Communication and Wakeup)
U801
Revision Overview
Level
Rev. 1.0: Initial Block Diagram
Shift
Rev. 1.1: updated U700 Memory size
4
Rev. 1.2 updated MISOB information,updated information at
U950 Headset detect circuit, updated information at U50 /
IPC_BCM
Key-Matrix
Rev. 1.3: RX signal name#s change + Pins on U50
0-9,*,#
Navigation,
Smart,
Volume
Servive, Engineering & Optimization 2006.12.1
LEVEL 3 AL Block Diagram Rev. 1.3
K1
K1
Page 1of 2
(Transmitt Enable)
(PA Power Control)
TX_EN
VDETECT
LB_HB
US_EURO
TX_ANT_SW_EN
IPC_BCM
TX_START
VRAMP
RESETB
(Transmitt Enable)
RX / TX
In / Out - Put controler
Synthesizer
Clock
Serial
RX / TX
Interface
(clock)
(framesync)
OWB
CLK 13 MHz
(from J5000 via J2 )
BB_SPI_MISO
BB_SPI_MOSI
AUL_CS
AUL_INT
GRAPH_INT
STANDBY_1_5V
BB_SPI_CLK
BLUE_RTSB
BLUE_WAKEB
BLUE_TX
BLUE_CTSB
BT_RESET_B
KBC0-2
BLUE_HOST_WAKEB
KBR0-7
USB_VPIN
USB_XRXD_RTS
USB_VPOUT_TXD
USB_VMIN_RXD
USB_TXENB
USB_SE0
BLUE_RX
BB_SAP_RX
BB_SAP_TX
BB_SAP_FS
BB_SAP_CLK
(13 MHz)
One Wire data from Battery
(Watchdog)
ATI_RESETB_2_7V
RESETB
RESET OUT
CLK 32KHZ
STANDBY
(to Atlas )
(to J2)
(from Atlas)
(to U700)
(to Atlas)
WDOG
(from Atlas)
Daughter Board
Flip Connector
J6 J27
FLIP CONNECTOR
U1501
7
11 SDC0DQ0
J2
EL Driver
8
13 SDC0DQ1
8 EL_LAMP_VP
EL_EN 3 1
SDC0DQ0 50 49 CLK_32KHZ_2_7V
1 SDC0DQ2
GND
2 (SD Card Data SDC0DQ2 48 47 GND
3 SDC0DQ3
VBOOST 10 from/ to Daughter
46
SDC0DQ3 45 GND
3
5 SDC0CMD
Board Conn. J27)
44 (SD Card Clock from U5000)
SDC0DQ1 43 SDC0CLK
EL_LAMP_VM
5
9 SDC0CLK
41 GND
GND 42
4
TF_VDD 7 PERIPH_IO_REG
Q2000 40 39 LCD_DATA3
LCD_DATA7
LCD_DATA4 38 37 LCD_DATA0
(LCD Data from Neptune)
12
TF_ENABLE (LCD Data from Neptune)
LCD_DATA1 36 35 LCD_DATA5
LCD_DATA2 34 33 LCD_DATA6
J4
32 31 SDC0CMD (SD Card Command from U5000)
GRAFX_REG_FL
1
8
SIM_DIO (fitered VCC from Atlas)
CAM_AVDD_FL 30 29 GND
2
2
SIM_CLK GND 28 27 BB_SAP_RX
(interupt from U5000
3 26 25 BB_SAP_TX (Control Bus for ATI
6 GRAPH_INT
VSIM
to Neptune)
from/ to Neptune)
24 23 BB_SAP_CLK
4 LCD_WEB
4
SIM_RST
(LCD Control 22 21 BB_SAP_FS
LCD_OEB
5
14..
GND
from Neptune)
(from Atlas)
20 19 PERIPH_IO_REG
LCD_CS
6
(from Atlas)
18 17 VBOOST
LCD_RS
16 15 GND
10 CAM_DIG_REG_FL
RTC_BATT
(fitered VCC from Atlas)
+
14 13
VBUCK_FL BLED_SINK3
RTC
12 11
(on PCB) GND BLED_SINK1
(to Atlas)
10 9
Strip Line BATT (from Atlas) IO_REG BLED_SINK3
Bluetooth
Antenna (from Neptune) 8 7
ATI_RESETB_2_7V
BLED_SINK4
6 5
(from Atlas) LEDB1
GND
(from J1) 4 3 HAND_SPKRM
VBUS
(from Atlas)
Bluetooth (from Atlas)
CHRGLED 2 1 HAND_SPKRP
PERIPH_IO_REG B3...... g1- g4
(from Atlas) GND
BP H6
BLUE_RX E5
BLUE_TX E4
25
(from/ to Neptune
BLUE_CTSB E8
(from/ to U301 BT, Serial Audio for Ringtone
BLUE_RTSB E7
Neptune - BT - Neptune and Voice Audio)
Communication and Wakeup)
H1
C8 U301
BLUE_WAKEB
H2
BLUE_HOST_WAKEB C6 Neptune Atlas
BB_SAP_RX
USB/ RS232 Charger and Power-
C4 C7 BATT CONN.
STANDBY
Communication
BB_SAP_FS (framesync)
source Control
BT_RESET_B E3
A7
BB_SAP_CLK(clock) J3
(to U250)
BT_CLK_EN D7
B6
BB_SAP_TX
(from U250) E2 Charger
BT_CLK
3 2 4 1
C7
(from Atlas) F6
CLK_32KHZ
(from Acesory Connector)
(EXT Power)
VBUS
VR1201
(One Wire Bus
to Neptune)
OWB GND
(toNeptune)
T14 SIM_PD
L10 CHRGLED(toFL3002)
M1401
13 Bit SAP (tx) (rx) C15 CHRGRAW
(VBUS Sense)
PRI SPI
2 V10
ALERTM USB/RS232 CNTL. ON AD
PCB ESD P13
(Bias Voltage from
Alert CODEC TOUT12
THERM THERM
NeptuneAtlas LOGIC
ALERT D14 Neptune)
ALERTP Amplifier 16 BIT (Battery Sense)
1 FL1400 U8 BATTP
Pads (communication) Neptune Atlas LOGIC CONV.
STEREO
F13 (Batt Current)
Communication ISNS
D/A
U14
Handset
HAND_SPKRM T6
(to J2)
Amplifier (Charger Current + )
E15 CHRGISNSP_PM
HAND_SPKRP R7
Q905 (M1) S
P9
4 MICBIAS1 G
Internal Color definition only for this section !
MIC Microphone
CHARGE
3 MICINM
T9 (Current Control) Main Charge Path
B16 CHRGCTRL
Supply R910 R911
CONTR.
B+ support without Ext Charger
D
Amplifier B+ support with Ext Charger
S
Q906 (M2) G D
G
Headset
SQ904 (M3)
(Main Source
NC B12
BATTFET
BP
Amplifier
Logic for Atlas)
BPFET_PM
B14
Stereo Battery to BPLUS
NC
D
Det. Switch
G
C6 BLED_SINK1
Mini USB Headset Q903 (M4)
NC LED
B6 BLED_SINK2
Det.
CNTL. (from FL3001)
D6 BLED_SINK3
S
(to Charging Circuit)
1 VBUS
F8 BLED_SINK4 VBUS to BP
Switch
(from Mini USB Connector)
(from Atlas) VBOOST B4 VBUS 5V
U900
D903
ESD (EXT Power)
(PPD device support) Pass FET VBUS
VR960 VBUS D2 D12 (from J1300)
RTC_BATT
ATLAS UL
V17
USB
(Accessory Detection signal)
H8
4 USB_ID
VR1203
EMU Y900
F3
DM_TXD
2
VR1212
J1
V16
Interface
E3
DP_RXD
3
VR1212 (to Neptune and U301 BT)
R16 CLK_32KHZ
(to J1300)
P16 CLK_32KHZ_2_7V
5 TIMER
(from Neptune)
Headset detect circuit CLK 13 MHZ
V12
(from Neptune)
WDOG
G1-G4 K10
U950
TX_EN_SW(from Neptune, Tx Mode indication for Atlas)
U15
(Shield) (Bias from Atlas)
R950
PERIPH_IO_ REG
(to U250)
STANDBYB
P14
(100K Headset
(from U800)
STANDBY
F12
detect Resistor)
(to Neptune, U250)
E12 RESETB
EMU_HDST_DET
(Headset detect Enable from Neptune)
4
3
1
Revision Overview
1
Rev. 1.0: Initial Block Diagram
Rev. 1.1: updated U700 Memory size
Servive, Engineering & Optimization 2006.12.1
JVIB
Rev. 1.2 updated MISOB information,updated information at
U950 Headset detect circuit, updated information at U50 /
LEVEL 3 AL Block Diagram Rev. 1.3
2
IPC_BCM
K1
Rev. 1.2: RX signal name#s change + Pins on U50
K1
Page 2of 2
FL1200
G1-G3
Transflash
Daughter Board Connector
SIM
FL3001
FL3002
BT_ANT
FL301
(rx)
(Bias)
PERIPH REG
AUL CS
USB_VPIN
USB_VPOUT_TXD
USB_TXENB
BB_SAP_TX
BB_SAP_FS
BB_SAP_RX
(tx)
BB_SAP_CLK
BATTP
R905
R4
R5
B3
E4
USB_SE0
C4
USB_XRXD_RTS
F4
P4
R3
B2
B1
USB_VMIN_RXD
F14
PWR_SW
T17
BB-SPI_CLK
T18
BB_SPI_MOSI
N14
AUL_INT
U18
U16
BB_SPI_MISO
REG
REG
VCO
REG
REG
VSIM
Switcher
Switcher
IO REG
AUDIO
B+ Sense
PERIPH
IO REG
GRAPH
RF REG
RF REG
to Vibrator
DIG REG
REF REG
REF REG
Buck 350mA
CAMERA
VIB REG
Boost 300mA
P2
Motor
N5
H3
H3
K17
U6
H2
F16
G16
R17
K11
F3,E13........
Q910
VCO_DRV
V2
( 1,3V )
VVIB
BP
VSIM_EN
( 1,2V )
REF_1P2
( 2,775V )
PERIPH_IO_ REG
(2,775V )
VM_REG
( 2,775V )
RF_REG
( 2,775 )
IO_REG
( 1,8/ 3V )
VSIM
( 2,775V )
AUD_ REG
( 1,575V )
REF_REG
L16
( 1,275 )
GRAFX_REG
M18
( 5,5V )
VBOOST
( 1,875V )
VBUCK
( 1,8V )
CAM_DIG_REG
P18
(to J2)
(from U800)
(to U250)
(to U250)
( 2,775V )
VCO_REG
(to U250)
(to Neptune)
(to AL + RF))
(to AL + RF))
(to AL + RF))
J3500, U1501)
(only used in Atlas)
(to J2, J1000, D1000
(to Neptune amd J27)
(to J2, J1000, J2000)
(Main Source- from Q904)
(to J2, J1000, Q2020)
( 2,775 )
CAM_AVDD
H4
(to U50,U250)