GSM 1800 RX
Low Channel - 512 = 1805.2Mhz
(Tx Enable)
Mid Channel - 700 = 1842.8Mhz
T/R Switch GSM_TXEN
High Channel - 885 = 1879.8Mhz (VCC)
Control
VRF
U103
EGSM RX
U102
2
6
1
Low Channel - 975 = 925.2Mhz CALIBRATION
(Tx /Rx selection) CH 62 RX Mode
1
Mid Channel - 37 = 942.4Mhz AP2
RF PORT
TRENA
RFLO= 947.3Mhz RX IF = 100kHz
3
High Channel - 124 = 959.8Mhz 3
4
GSM 1800 TX
U201 U203
TX / RX Switch
947,4 MHz 4
22
Low Channel - 512 = 1710.2Mhz 12
1 ION
CH 62
2
11
U101 2 4
Mid Channel - 700 = 1747.8Mhz
RXIP
F101 ADC 2 IOP
PGA 5
ADC
High Channel - 885 = 1784.8Mhz 6 21
Control
RXIN
11
Function
2 IF/100kHz
1
EGSM TX
4
10 20
GSM_RX 925-960MHz
Low Channel - 975 = 880.2Mhz
4
CKP 9
2
2
8 Duplexer
Mid Channel - 37 = 897.4Mhz RXQP
JP1
1 1805-1880MHz
DCS_RX ADC CKN
F102 3 3
PGA ADC
6
19
High Channel - 124 = 914.8Mhz
1 RXQN
10
2 6, 12
RF ANTENNA
100kHz
SPI
3 5 0
14, 23, IF
90 1
26, 32
N
6, 20
13 18 17 16 5 14
TX /CH 62
7
1301.4 MHz
PA
13Mhz VRF
GSM 6
399MHz 399MHz TXIN
1
GSM_TX 25
9
GSMPA PHASE
7
2 1 Exc.
R402 5
DET.
2
TXIP
CMOS
DCS
8
DCS_TX
11 1
24
DCSPA
TXQN
2 1 Exc.
R403
7
TXQP
TX/ CH 62
902,4 MHz
6 APC (Power Control)
12 13
9 10
U401
3 PAENA(Enable)
Control
2
GSM_TXEN(Band Select)
4 VSYN
(VCC)
VBAT
RX /CH 62
1894.6 MHz
5, 25, 28
(Data in)
RF_DAT
13
798 MHz
(Clock in)
RF_CLK 24
12 SPI
RF
CH 62
(Latch)
RF_LE
(from/to U15) 23
11 IF
VCO
(Data out)
SDO_RF
10
27
IFLOP
(Enable) PDNB 9
IF
26 IFLON
(VCC)
1
VCC4 VTCXO VCO
5
7 U301
13Mhz
U503
U105
4
5
(Enable) 2
TCXOEN 3
(VCC) CH 62 TX Mode
7
VBAT VSYN (Tuning/Bias)
8
13Mhz_BB
RFLO= 1301,4Mhz
U104 (VCC)
3
AFC IFLO= 798MHz
(Enable) VRF VTCXO 4 1
SXENA 3, 5 6
U302
TX VCO = 902,4 MHz
GSM SERVICE SUPPORT GROUP 2003.05.19
REFERENCE CLOCK
RX SIGNAL PATH
LEVEL 3 RF Block Diagram Rev. 1.2
Orderable Part
TX SIGNAL PATH
Revision Overview
Dual Band - E365
Rev. 1.0: initial Block Diagram
Rev. 1.1: updated SDO_RF signal direction, updated U303 to U503
MAIN VCO SIGNAL PATH Non - Orderable Part
Rev. 1.2: updated F1 as EMI filter, RF VCO frequency, U201 internal divider, U503 output, TR Switch Michael Hansen Page 1 of 2
TUNING VOLTAGES
Filter
Channel
o
o
RF_CLK
RF_LE
PDNB
TCXOEN
RF_DAT
SDO_RF
(Data out)
(Enable)
(Data in)
(Clock in)
(Latch)
(Enable)
RFLOP
RFLON
Dual Band E365
CAMERA
RF_DAT
H11
DISITAL CAMERA
A5,B12,F11,M1,N14,P7
RF_CLK
VRDBB1.5V Hercules U15 J14 Connector
IC
Camera
A11,L14,N3,N1,N5
POWER H14 RF_LE
J1
VRIO_2.8V B9
Analog / Baseband eventuell verbunden auf RF!! U203, U301 RNW DATA BUS DD 0-7
J6
A4,B6,D1,G1 SDO_RF
DLPWR B10
VRMEM_2.8V nFOE
U18
F1
L12 PWDN 4
PDNB
VACCID G13
SIO3
nCS4 B10
RX/TX D33V 5
K14 GSM_TXEN H4 SCK
10
G10
SRST3
to/ from Omega SIM
CLK13M_DSC
CNTL
3 K13 TRENA E9 SDA
TDI Regulator 8
SCLK3 F13 CLK13M_OUT 2 3 4
U12
M14 (to RF Side) D9 SDO
14 TCK PAENA 20
A13 E10
15 TMS TDO, TDI, TMS, TCK JTAG SXENA Regulator SCLK 9
DATA BUS D0-7
5 TDO A12
TCXOEN U8
K3 SHS 2
7 CTS_MODEM C9 CAMERA (to/ from Hercules)
(VCC) (to Flash)
VCC4 1 F_1.8
J4
SVS
3
8 RX_MODEM A9 Switch ADD BUS A1-3
F10
B13 SPCLK
VDDS-MIF_2.8V 5
VRRAM_2.8V 2,3 9
9 U14 G1, ......
TX_MODEM B9 RTC
D25V
(to U19, Q1, J2)
A14
(enable)
10 UART S22
E8 ROW4 6 L2, ...... S25V
RTS_MODEM ARM 7 ON/ D33V 6
CLK32K_OUT
C12
11 D9 OFF COL4 B4 DD25V 7
DSR_MODEM
AVDDP
B14 RTC_ALARM
12 DTR_MODEM N3 CNTL
AVSSP A4
GND 1
F10 SWITCHONOFF Regulator
6 Rx_IrDA D8
D12
RESPWRONZ U13
4 Tx_IrDA C8
D14
VRRTC (VCC) 1 9 J5
VBAT D33V
VBAT-VCHG 5 1
TFTConnector
TFT Display
VBAT
13 M10
COMS_EN
10 DD25V
2,3
U9
4 1
C11 nCS4 1,2
NC
1 VCHG IO_PWR_EN
L8 S25V
(from ext. charger)
C1 nCS2 6 LCD_ID 3
RR26 D25V
KeyLed_En L7
L4 LEDLCM_EN GND 4,5
I/O
GPIO
AVDDP
EAR_DETECT N11 L6
L8 LCD_ID nCS2 6
U19
AVSSP
M4 LCDA0 L7 LCDA0 7
(enable) nCS2
(from U303) RNW 8
13MHZ_BB E13
nBLE U7
E4 (VCC)
A1 VDDS-MIF_2.8V 5 3 4 LCD_RD
CLK13M_OUT 9
2M RAM nBHE DATA BUS
SRAM
F5 B2
D0-D12 10-22
(to Display) nRESET
DATA BUS
RNW
D13-D15 28-26
G5 ADD BUS
MEM
nFOE
TIMER VDDS-MIF_2.8V 23,24
nRESET
VRIO_2.8V N2 A2
I/FACE
D6, E1, A6
VRRAM_2.8V
Boost Power
nRESET 25
F12
VBAT CLK13M_OUT
RNW (VCC) VBAT FL1
LED_Anode 29
nIRQ_Melody B2 C5 (Write Enable)
H10
nFOE
D6
E2 F8 (Output Enable)
LED_Cathode 30
FDP
U11
15 7 4 1 3 29
K8 (Reset)
B5
SDO F4
3 2
30 DAI 1
nSCS0 L9 A22
U10 nCS0
LS1 17
C2 CE U6 (enable) LEDLCM_EN 4
BL1 31
4 1 Melody IC P9
SCLK Digtal Audio nCS3 U20 E7
SPKR 18 FLASH 2 R36
D3
32 M9
SDI Interface
DSP MEMORY
AUXO 12,13,14 DATA BUS
A5, A4, G4
F_1.8
N12 ADD BUS
VCLKRX
E1,G6, D6, B4
VRMEM_2.8V
VDX P14
Key
VOICEBAND J1/ J2
COL 0 - COL 4
VDR N13 board
Radio
Keyboard
SPI
Interface Int.
Int. Kepad
VFSRX
M13 ROW 0 - ROW 4
Connector
F11 Main Charge Path
N7, M7, M8
Charger Overvoltage Protection
1-5
COL 0 - COL 4
VRDBB1,5V
Battery Over Voltage Protection
BDR/ BFSR ROW 4 - ROW 1 15-12, 7
BDX/ BFSX (Sense)
PCHG
Light
D2 Sensor
VDDS-MIF_2.8V
VCCS 8
VBAT
(to Batterie)
(from J1)
VCHG
R1
Ext.
Q1
VBATS On/Off
Charger
U2
(Sense) 5 Switch 4, 5
LIGHTSENSER_EN
11
VRAM_2.8V
D S S Ext.
3 1 1
(Charge Current Control)
G U3 Overvoltage
ZD1 Backlights
ICTL G nCHG Control
B D
J5, K5, K6
18
D9 TXIP
2 6
(bulk)
VBAT
RTC BATTERY BT1 VBACKUP
SPI BASEBAND D10 TXIN
E1
(to U1, U5)
(to U201) VCHG1 D2, D3
BACKUP C10 TXQP
A1,A2,G2,G9,K1 UPLINK
D6, D7
(from U4/ D3) VCC4
BQ3
C9 TXQN
D8, D9
LEDKEYN
BASEBAND
VRABB_2.8V H10 BASEBAND - 2.8V 3
SERIAL F9 RXIP KeyLed_En 2
(VCC) 16
BASEBAND Regulator
VRDBB_1.5V J1 BASEBAND - 1.5V 1 1
PORT F10 RXIN
(fromU203)
D3
VRIO_2.8V B1 IN/ OUTPUT- 2.8V E10 RXQP
DOWNLINK
VRRAM_2.8V E9 (to U1 as U5
F1 RAM - 2.8V RXQN VCC4
EMI Filter Main Soure
VRMEM_2.8V MEMORY - 2.8V for Regulators) LEDB
G1
E4
TSP CLK13M_OUT
1
2
VBAT D1 RTC - 1.5V OMEGA U1
VRRTC_1.5V
F1
C5
VBATS
2
A4
VBATD
VCHG1
Sense S19
BATTERY PWON 6
(ON/OFF)
3 A5
VCHG1
VIBRATOR
Battery CONNECTOR
1 2 D5 VCCS
DAC 1
Batterie
H4 IO
M1 BQ1
D6 PCHG
(Sense) J3
Switch
AFC AFC
J4 (Charge Current Control)
B5 ICTL
(to RF Side) Charger
U4 VBAT
VBATD R16 1
K4
APC APC
Interface
2
IBIC
BATTEMP
3
B 2
1 HSMICBIAS
Sense
2
BUS
3 C K8 E7 BS_TDO
2
E Auxi2 HSMICIP NC
RX SIGNAL PATH
K7 CNTL D7 TDI
JTAG
BQ4 MICBIAS
U16 4 BATTGND
J8 E8 TMS
VOICE
3
Batterie
TCK
4 D8
MICIP TX SIGNAL PATH
1 5 J7
J4 UPLINK
MIC1 EF2 Over Voltage
5
5
Audio MICIN H7
EF1 VCLKRX
3 4 USP K3
Protection
3
Jack 2 MAIN VCO SIGNAL PATH
EARP
Micro Proc.
LS2 F5 VDX
J9
(to/ from Hercules)
BL2
EARN
VOICE 5,6
Ser. Port G5 VFSRX
1
SPKR J10
U17
GND
TUNING VOLTAGES
HSO
H5 VDR
DOWNLINK
H9 7, 8
Switch
E5
(to U10) K9
AUXOP
S_IO
REFERENCE CLOCK
SIM I/Face G4
SRST3
(to/ from Hercules)
(from U15)
CLK32K_OUT E2 3V / 5V F4
Orderable Part
SCLK3
(to U15)
E3
SWITCHONOFF
LEVEL
SCLK5
ADC C4
VRPC
(to U15) D3
RESPWRONZ
1
Volt. Reg. and Analog/Digital SHIFTERS SRST5 SIM CON.
D4 Non - Orderable Part
(from Keyboard) F8
PWON
3
Power up Ctnl. Converter SIO5
D2
(from U15) RTC_ALARM B3
2
CON1
(Ext./ on from J1) F7
DLPWR
VR_1.8/2.9VSIM
B4
5
A10 B6C7
A6C6
GSM SERVICE SUPPORT GROUP 2003.05.19
LIGHTSENSER_EN
LEVEL 3 AL Block Diagram Rev. 1.2
BATTEMP
Revision Overview
VBAT
Dual Band-E365
Rev. 1.0: initial Block Diagram
VACCID
Rev. 1.1: updated SDO_RF signal direction, updated U303 to U503
LEDB
Rev. 1.2: updated F1 as EMI filter, RF VCO frequency, U201 internal divider, U503 output, TR Switch Michael Hansen Page 2 of 2
RR1
MCUDI
MCUDO
MCUEN0
EAR_DETECT
BATTGND
Dual Band E365