RX MID CHANNELS
850: CH190 -- 881,6
GSM: CH 62 -- 947,4 MHz
Internal
EGSM: CH 37 -- 942,4Mhz
Antenna
DCS: CH 700 -- 1842,8MHz
VCO_REG
M1
PCS: CH 661 -- 1960MHz
PA + Antenna Switch
18,31
ANT_DET_B (indicates mechanical Antenna connection to U800)
DCS/PCS OUT
TX_HB 25
J7506 Mechanical
4 2
RA61 1 2 3
Antenna Switch
6
11,14....
BP
2 TX_LB 26
4
1 2 3
RA60 Power and
Antenna
GSM850/
Control
GSM900 OUT
U50 - RAPTOR 8 17 BP
1 4 16 15 9 13
2 3 10
5,6
1900 MHZ
Switch
3 2
REG_BYP_CORE
U807 (Enable)
IO_REG
M18
NEPTUNE LTE2
1800 MHz H1 IO_REG (VCC + 2.775V)
U800
PA Power Control selection via VRAMP, TX_HB and TX_LB
(VCC + 2.775V)
A11, U16, ..... PERIPH_IO_REG
DSP Peripherals Power
(VCC + 1,575V)
1. IPC: Input Power Control mode - for EDGE mode E2 REF_REG
accelerator, encryption
900 MHz (PA gain is fixed and PA input power varies) V5, R16, .... VBUCK
(VCC + 1,875V)
Timer, Interupts
(from Atlas )
VSIM
2.BCM: Bias Control mode - for GMSK mode
K2
(Data In /OUT)
SIM DIO
(PA gain varies according to power step and fixed input PA power)
850 MHz
K3
SIM RST (Reset )
U6 L1 Timer DSP
SIM
DSP J4
(from / to JDaughter Board Connector
Memory
UltraLite Interface SIM CLK (Clock )
L1
104 MHz
SIM_PD
R1
(from Atlas )
(to Atlas)
M1 VSIM_EN
D0-15
DATA BUS
Shared Memory
A0-23
1Mbit RAM
ADDRESS BUS
GSM / EDGE Tranceiver IC
FL100
A1
Quard Saw Filter A4 B3 C3 C2 A2 B2 E2 B9
W18 CS0BA K1
U700
N10
and Matching
MCU V17
U250 -TRANSAM External CS1BA G8
14 K12 MCU
PA Control GPIO G1 STANDBYB Memory
1 W10 T18 CS2B D6
ARM7
Memory
LNA
High Band 15 L12
52 MHz
GPIO G17 EB1B F3
1900MHz U9
Interface
FLASH
K16 EB0B C2
12 G12
3
T8
G2 DRI (Data TX)
LNA J19 F4 RESET OUT (from Neptune)
R_WB
High Band 13 H12 F5,D5
LPF
1800MHz Digital Radio T16
OEB
D1 J2,H1,H8
MS (TX/RX Enable)
(from Atlas)
10 D12 DC E4... VBUCK
T19 BURSTCLK C6
26 MHz
A4
4 Correct Receiver Clock Generator
LBAB E5
L16
E3 (Data RX) Oscillator
Low Band LNA MDI
11 E12
N18 ECBB G7
900MHz
16 MB SRam
8 A12 MISOB (readback)
G3
RX CP 64 MB Flash
6 (only used in Engineering debug mode
Low Band LNA ÷4
9 B12 LCD_OEB
- not for Service) D14
850MHz 90° MQSPI
LCD_RS
P2
RX VCO Display
LCD_CS
N3
(LCD Control to U5000 )
L8 ÷2 F3
MCLK ATI_DQ (0 - 7)
L3...
90°
J1
LCD_WEB
BT_CLK D18
L10 J3 BT_CLK_EN
(indicates mechanical Antenna connection to U800)
ANT_DET_B
U12
1
TX VCO
TX CP K4 2
(Bias output for THERM signal)
Y100 U10 TOUT12
÷2
3
K5 26MHz (EL Backlight Enable to U1501)
N9 EL_NAV_EN
(Trans Flash Enable to J4, Q2000 )
(Data In /OUT) TF_ENABLE
GPIO W8
D2 RF_DATA
U8
Phase Modulation
(Clock ) (U250 Control Bus)
(to Atlas U900)
NEP_CAM_TOURCH_EN
F1 T6
RF_CLK
V7 SPI
(Chip select)
÷2
(to Atlas U900 )
E1 EMU_HDST_DET
RF_CS W9 A12
On (to Atlas U900)
AD_TRIG
A12
Off
C10
VCO_REG
J5, J8
VM_REG
One BaseBand UART2 Hall Effect
ADC
LPF LPF
UART / USB
Transmit H2 VBUCK Timer
Keypad Serial Audio Inverter
Wire Universal
(VCC s from Atlas)
Voltage B4 MQSPI
RF_REG Interface Port Interface
Modulator
BT
Amplitude Modulation Interface Interface Bus Asynchron. 2
4 1
C1 (Flip Open/ Close
Reg. IO_REG
HS INT
(rx) (tx) C14 U1401 U1600
Rx /Tx
Detect)
C5
REF_1p2
A17 C15 D15 F3.... V12 W12 V13 E3 U11 A12 B13 N13 D16 B15
5 6
F2.... W13 D13 N17 V16 D19 T7
B16 C16 A16 T11 T10 W5 W11 B12
V11 B14 G8 U13
PERIPH_IO_REG
Neptune Atlas Neptune Atlas (from/ to U301 BT, J1300
(from/ to Neptune
USB/ RS232 Communication Serial Audio for Ringtone Neptune - BT - Neptune
2
Communication and Voice Audio) Communication and Wakeup)
U801
FL1501
Level
FL1502
Shift
EMI & ESD
4
Revision Overview
Rev. 1.0: Initial Block Diagram
updated EL Circuit to U3000
Key-Matrix
0-9,*,#
Navigation,
Smart,
Volume
Camera
Servive, Engineering & Optimization 2006.11.02
LEVEL 3 AL Block Diagram Rev. 1.1
Z3
Z3
Page 1of 2
(Transmitt Enable)
(PA Power Control)
TX_EN
VDETECT
LB_HB
US_EURO
TX_ANT_SW_EN
IPC_BCM
TX_START
VRAMP
RESETB
(Transmitt Enable)
RX / TX
In / Out - Put controler
Synthesizer
Clock
Serial
RX / TX
Interface
(clock)
(framesync)
OWB
CLK 13 MHz
(from J U5000)
BB_SPI_MISO
BB_SPI_MOSI
AUL_CS
AUL_INT
GA_INT
STANDBY_1_5V
BB_SPI_CLK
BLUE_RTSB
BLUE_WAKEB
BLUE_TX
BLUE_CTSB
BT_RESET_B
KBC0-2
BLUE_HOST_WAKEB
KBR0-7
USB_VPIN
USB_XRXD_RTS
USB_VPOUT_TXD
USB_VMIN_RXD
USB_TXENB
USB_SE0
BLUE_RX
BB_SAP_RX
BB_SAP_TX
BB_SAP_FS
BB_SAP_CLK
(13 MHz)
One Wire data from Battery
(Watchdog)
ATI_RESETB_2_7V
RESETB
RESET OUT
CLK 32KHZ
STANDBY
(to Atlas )
(from Atlas)
(to U700)
(to U5000)
(to Atlas)
WDOG
(from Atlas)
EL Backlight Driver
U3000
EL Driver
(enable from Neptune)
8 EL_LAMP_VP
EL_NAV_EN 3
VBOOST 10
EL_LAMP_VM
(on PCB)
Strip Line
Bluetooth
Antenna
Bluetooth
PERIPH_IO_REG
B3......
(from Atlas)
BP H6
BLUE_RX E5
BLUE_TX E4
25
(from/ to Neptune
BLUE_CTSB E8
(from/ to U301 BT, Serial Audio for Ringtone
BLUE_RTSB E7
Neptune - BT - Neptune and Voice Audio)
Communication and Wakeup)
H1
C8 U301
BLUE_WAKEB
H2
BLUE_HOST_WAKEB C6 Neptune Atlas
BB_SAP_RX
USB/ RS232 Charger and Power-
C4 C7 BATT CONN.
STANDBY
Communication
BB_SAP_FS (framesync)
source Control
BT_RESET_B E3
A7
BB_SAP_CLK(clock) J3
(to U250)
BT_CLK_EN D7
B6
BB_SAP_TX
(from U250) E2 Charger
BT_CLK
3 2 4 1
C7
(from J600)
(from Atlas) F6
CLK_32KHZ
(from Acesory Connector)
(EXT Power)
VBUS
VR1201
(One Wire Bus
to Neptune)
OWB GND
(toNeptune)
T14 SIM_PD
L10 CHRGLED(toJ600)
M1401
13 Bit SAP (tx) (rx) PRI SPI C15 CHRGRAW
(VBUS Sense)
2 V10
ALERTM USB/RS232 CNTL. ON AD
PCB ESD P13
(Bias Voltage from
Alert CODEC TOUT12
THERM THERM
NeptuneAtlas LOGIC
ALERT D14 Neptune)
ALERTP Amplifier 16 BIT (Battery Sense)
1 FL1400 U8 BATTP
Pads (communication) Neptune Atlas LOGIC CONV.
STEREO
F13
Communication (Batt Current)
ISNS
D/A
U14
Handset
SPKRM T6
(to J2)
Amplifier (Charger Current + )
E15 CHRGISNSP
SPKRP R7
Q905
S
P9
4 MICBIAS1 G
Internal Color definition only for this section !
MIC Microphone
CHARGE
3 MICINM
T9 (Current Control) Main Charge Path
B16 CHRGCTRL
Supply R910 R911
CONTR.
B+ support without Ext Charger
D
Q906
Amplifier B+ support with Ext Charger
S
G D
G
Headset
SQ904 (M3)
(Main Source
NC B12
BATTFET
BP
Amplifier
Logic for Atlas)
BPFET_PM
B14
Stereo Battery to BPLUS
NC
D
Det. Switch
G
C6 BLED_SINK1
Mini USB Headset Q903 (M4)
NC LED
B6 BLED_SINK2
Det.
CNTL. (from J600)
D6 BLED_SINK3
S
(to Charging Circuit)
1 VBUS
VBUS to BP
F8 BLED_SINK4
Switch
(from Mini USB Connector)
E10 LED_BT
(from Atlas) VBOOST B4 VBUS 5V
U900
D903
ESD (EXT Power)
(PPD device support) Pass FET VBUS
VR960 VBUS D2 D12 (from J1300)
RTC_BATT
ATLAS UL
V17
USB
(Accessory Detection signal)
H8
4 USB_ID
VR1203
EMU Y900
F3
DM_TXD
2
J1
V16
VR970 Interface
E3
DP_RXD
3
R16 CLK_32KHZ (to Neptune and U301 BT)
(to U5000)
P16 CLK_32KHZ_2_7V
5 TIMER
(from Neptune)
Headset detect circuit CLK 13 MHZ
V12
(from Neptune)
WDOG
G1-G4 K10
U950
(from Neptune, Tx Mode indication for Atlas)
ADTRIG (TX_START)
U15
(Bias from Atlas)
(Shield)
R950
PERIPH_IO_ REG
(to U250)
STANDBYB
P14
(100K Headset
(from U800)
STANDBY
F12
detect Resistor)
(to Neptune, U250)
E12 RESETB
EMU_HDST_DET
(Headset detect Enable from Neptune)
4
3
1
2
VIB Motor
2
1
Revision Overview
Rev. 1.0: Initial Block Diagram
updated EL Circuit to U3000
Servive, Engineering & Optimization 2006.11.02
LEVEL 3 AL Block Diagram Rev. 1.1
Z3
Z3
Page 2of 2
BT_ANT
FL301
(rx)
(Bias)
PERIPH REG
AUL CS
USB_VPIN
USB_VPOUT_TXD
USB_TXENB
BB_SAP_TX
BB_SAP_FS
BB_SAP_RX
(tx)
BB_SAP_CLK
BATTP
R905
R5
R4
B3
E4
USB_SE0
C4
USB_XRXD_RTS
F4
P4
R3
B2
B1
USB_VMIN_RXD
F14
PWR_SW
T17
BB-SPI_CLK
T18
BB_SPI_MOSI
N14
AUL_INT
U18
U16
BB_SPI_MISO
REG
REG
VCO
REG
REG
VSIM
Switcher
Switcher
IO REG
AUDIO
B+ Sense
PERIPH
IO REG
GRAPH
RF REG
RF REG
to Vibrator
DIG REG
REF REG
REF REG
Buck 350mA
CAMERA
VIB REG
Boost 300mA
P2
Motor
P18
N5
K16
H3
K17
U6
H2
F16
G16
R17
K11
V3, J4........
Q910
NC
NC
NC
M18
VCO_DRV
V2
( 1,3V )
VVIB
BP
VSIM_EN
( 1,2V )
REF_1P2
( 2,775V )
PERIPH_IO_ REG
(2,775V )
VM_REG
( 2,775V )
RF_REG
( 2,775 )
IO_REG
( 1,8/ 3V )
VSIM
( 1,575V )
REF_REG
L16
( 5,5V )
VBOOST
( 1,875V )
VBUCK
(from U800)
(to U250)
(to U250)
( 2,775V )
VCO_REG
(to U250)
(to Neptune)
(to AL + RF))
(to AL + RF))
(to AL + RF))
(to Neptune amd
Daughter Board)
(to JJ600, U3000
(to J2000, Q2020)
( 2,775 )
CAM_AVDD
H4
(Main Source- from Q904)
(to U50,U250)
(Neptume / ATI
Communication Bus
Tri Flash Write Data)
ATI
Graphics Accelerator
J400 Camera /Display
Pogo Pins for
Camera Flash Connector
U5000
(VCC from Atlas)
4
B+
SPI
J2
1 FLASH_TORCH_EN
GND 2 GPIO
TP712_EL_COM K2
3 FLASH_DRIVER_EN
EL Main PCB Contact
TP_EL2
BB_SAP_CLK W2
CLK_32KHZ_2_7V
Timer U19
(ATI- Neptune
BB_SAP_FS V1
Serial
Tri-Flash -Neptune
BB_SAP_TX H7 VBUCK (GRAPH_REG)
J600 Communication) V2
Interface
BB_SAP_RX IO_REG
V4 V19
Slider Connector Power
A2...
PERIPH_IO_REG
U3000
R19...
GRFX_REG
10..... PWR_SW (to Atlas) CAMERA
EL Driver
CONNECTOR
(Enable from Neptune)
10.....
8 EL_COM KPR0-5
4
EL__NAV_EN 3
(from/ to Neptune) J2000 Q2020
18...
KPC1-2
(VCC) 10
VBOOST
EL2 B3 GPIO 5 Switch
6 CAM_AVDD
15 LCDC_SCLK 19
G1
LCDC_SDI
17 20 BUCK_SW 2,3 4
VBUCK
C1
19 LCDC_DO
B2
VBOOST 1 21 LCDC_CSB
R6 D_CAM(0) 5
(VCC from Atlas) D1
IO_REG 3 36 LCDC_RESETB
T6 D_CAM(1) 7
5
VBUCK U8096
G2 T7 D_CAM(2) 9
Serializer
F2 V6 D_CAM(3) 10
G3 SER_EN
Image Data
(from Mini USB)
VBUS 35
R7 D_CAM(4) 11
Output Enable LCDC_OE
B3 R2
CHRGLED 33 D_CAM(5) 12
(VSync) T1 T8
C3 LCDC_GS
LED_BT 23 Control R8 D_CAM(6) 13
Control R1
C4 (H Sync) LCDC_LS
D_CAM(7)
BLED_SINK4 7 P1 R9 14
B4 Data Clock LCDC_CLK
F1
BLED_SINK3 9 Serial Data LCDC_SD (Horizontal Sync) 2MP
A3 HS 15
W8
11 Camera
BLED_SINK2 (Vertical Sync) 16
(from Atlas) VS
V8
32 D1
SER_CLKP Sync.
13 G6 LCDC_RED5 J5
BLED_SINK1
CLK0 2
W6
30 E1 Serial
SER_CLKM
F5 LCDC_RED4 N2
CLKI 6
G1 W9
24 SER_DATAP
H4
G5 LCDC_RED3
SPKRP 27
26 F1
SER_DATAM
K4 CAM_SCL 1
SPKRM 29 E4 LCDC_RED2 W7
Parallel M2
G4 LCDC_RED1 CAM_SDA 3
V7
Control
VBUCK J5
F4 LCDC_RED0 23
L2 CAM_RESET
(VCC from Atlas)
M5
D4 LCDC_GREEN5
H1 22
CAM_PWRDWN
M1
D6 LCDC_GREEN4
KBR0 28
L5
D5 LCDC_GREEN3
Keys:
RGB Data
KBR3 26
K5
E6 LCDC_GREEN2
(from/ to 27
KBR4 Volume
L1
E5 LCDC_GREEN1
Neptune)
30
KBR6
Smart
L4
F6 LCDC_GREEN0
29
CBC2
M4 Voice Cmd
C6 LCDC_BLUE0
N1
C5 LCDC_BLUE1
N5
B6
LCDC_BLUE2
B5 P2
LCDC_BLUE3
N4
A6
LCDC_BLUE4 Daughter Board
P4
A5 LCDC_BLUE5
J4
C1,D2 GND
D19 SD0 11 7
D15 SD1 13
8
(LCD ID Resistor) SD2 1
SDIO C19
1
SD3 3
LCDC_PID1 G2 Interface B19
PERIPH_IO_REG R5002
GND
2
H2 GPIO (ID) D14 SD_CMD 5
LCDC_PID2
GND
E19 SD_CLK 3
9
5
14
TF_DET
R1209
4
TF_VDD
Q2000 TF_VDD
PERIPH_IO_REG 7
12
TF_ENABLE
1
8
SIM_DIO
2
2
SIM_CLK
(from/ to Neptune)
4 3
SIM_RST
15.. 4
GND
5
6
6
VSIM
(from/ to Atlas)
10
RTC_BATT
+
RTC
BATT
Revision Overview
Rev. 1.0: Initial Block Diagram
Servive, Engineering & Optimization 2006.10.10
LEVEL 3 AL Block Diagram Rev. 1.0
Z3
Z3
Page 2of 2
FL1200
Transflash
G1-G3
Daughter Board Connector
SIM
GA_INT
ATI_RESETB_2_7V
LCD_OEB
LCD_RS
ATI_DQ (0 - 7)
LCD_WEB
P19
E14
N19
P15
H19..
H16
B