> --
> -- VHDL Architecture RAM1_LIB1.automat.rtl
> --
> -- Created:
> -- by - ep.staff (herkules)
> -- at - 11:52:35 11/18/09
> --
> -- using Mentor Graphics HDL Designer(TM) 2008.1b (Build 7)
> --
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
> USE ieee.std_logic_arith.all;
>
> ENTITY automat IS
> port (clk, reset : in std_logic;
> nr, wr, zero, start : in std_logic;
> load : out std_logic;
> drive, sel: out std_logic_vector (1 downto 0));
> END ENTITY automat;
>
> --
> ARCHITECTURE rtl OF automat IS
>
> type stany is (idle, read1, read2, write1, write2);
> signal state, next_state : stany;
>
> BEGIN
> synchrP: process (reset, clk)
> begin
> if reset = '1' then
> state <= idle;
> elsif (clk'event and clk='1') then
> state<= next_state;
> end if;
> end process;
>
> kombP: process(state, nr, wr, zero, start)
> begin
> case state is
> when idle =>
> load <= '1';
> drive <= "00";
> if (start = '0') then
> next_state <= idle;
> sel <= "00";
> elsif (nr='0' and wr='0') then
> next_state <= read1;
> sel <= "10";
> elsif (nr='1' and wr='0') then
> next_state <= read2;
> sel <= "01";
> elsif (nr='0' and wr='1') then
> next_state <= write1;
> sel <= "00";
> elsif (nr='1' and wr='1') then

> next_state <= write2;
> sel <= "00";
> else next_state <= idle;
> sel <= "00";
>
> end if;
>
> when read1 =>
> load <= '0';
> sel <= "10";
> drive <= "00";
>
> if (zero='1') then next_state <= idle;
> sel <= "00";
> else next_state <= read1;
>
> end if;
>
> when read2 =>
> load <= '0';
> sel <= "01";
> drive <= "00";
> if (zero='1') then next_state <= idle;
> sel <= "00";
> else next_state <= read2;
>
> end if;
>
> when write1 =>
> load <= '0';
> sel <= "10";
> drive <= "10";
> if (zero='1') then next_state <= idle;
> -- sel <= "00";
> else next_state <= write1;
>
> end if;
>
> when write2 =>
> load <= '0';
> sel <= "01";
> drive <= "01";
> if (zero='1') then next_state <= idle;
> -- sel <= "00";
> else next_state <= write2;
>
> end if;
>
> end case;
> end process;
>
>
> END ARCHITECTURE rtl;
>
> --

> -- VHDL Architecture RAM1_LIB1.tst_bnch.test
> --
> -- Created:
> -- by - ep.staff (herkules)
> -- at - 13:00:40 11/18/09
> --
> -- using Mentor Graphics HDL Designer(TM) 2008.1b (Build 7)
> --
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
> USE ieee.std_logic_arith.all;
>
> ENTITY tst_bnch IS
> END ENTITY tst_bnch;
>
> --
> ARCHITECTURE test OF tst_bnch IS
>
> component top_ram IS
> generic (n: integer range 0 to 1024 := 7;
> l : integer range 0 to 255 := 2);
> port (reset, clk : in std_logic;
> nr, wr, start : in std_logic;
> data: inout std_logic_vector (n downto 0));
> END component top_ram;
>
> signal reset, clk: std_logic;
> -- deklaracje pozostaych sygnaów
> signal nr, wr, start: std_logic;
> signal data: std_logic_vector (7 downto 0);
>
>
> BEGIN
> T: top_ram port map(reset, clk, nr, wr, start, data);
>
> reset <= '1',
> '0' after 4ns;
>
> -- generacja pozostaych sygnalów testowych
>
> clock: process
> begin
> clk<= '0';
> wait for 0.4ns;
> clk <= '1';
> wait for 0.4ns;
> end process;
>
> start <= '0',
> '1' after 4ns;
>
>
>
>
> nr <= '0',

> '1' after 5600 ps,
> '0' after 19600 ps;
>
> wr <= '0' after 5600 ps,
> '1' after 10800 ps,
> '0' after 19600 ps;
>
> data <= "10101010",
> "11001100" after 5600 ps,
> "10101111" after 6400 ps,
> "00011011" after 7200 ps,
> "00111100" after 8000 ps,
> "00000111" after 8800 ps,
> "00001000" after 9600 ps,
> "11010000" after 10400 ps,
> "01100010" after 11200 ps,
> "ZZZZZZZZ" after 12000 ps,
> "ZZZZZZZZ" after 19600 ps,
> "00011010" after 20400 ps,
> "01010101" after 21200 ps,
> "00001111" after 22000 ps,
> "00111010" after 22800 ps,
> "00001100" after 23600 ps,
> "01010111" after 24400 ps,
> "00011111" after 25200 ps,
> "01110111" after 26000 ps;
>
>
>
>
> stopsim: process
> begin
> wait for 200 ns;
> assert false
> report "koniec symulacji"
> severity failure;
> end process;
>
> END ARCHITECTURE test;
>
> --
> -- VHDL Architecture RAM1_LIB1.top_ram.str
> --
> -- Created:
> -- by - ep.staff (herkules)
> -- at - 12:31:38 11/18/09
> --
> -- using Mentor Graphics HDL Designer(TM) 2008.1b (Build 7)
> --
> LIBRARY ieee;
> USE ieee.std_logic_1164.all;
> USE ieee.std_logic_arith.all;
>
> ENTITY top_ram IS
> generic (n: integer range 0 to 1024 := 7;

> l : integer range 0 to 255 := 2);
> port (reset, clk : in std_logic;
> nr, wr, start : in std_logic;
> data: inout std_logic_vector (n downto 0));
> END ENTITY top_ram;
>
> --
> ARCHITECTURE str OF top_ram IS
>
> ----deklaracje komponentów
> component reg1
> generic (n, m :integer :=7);
> port (data_in : in std_logic_vector (n downto 0);
> data_out: out std_logic_vector (n downto 0);
> clk, enable, drive : in std_logic);
> end component;
>
> component licznik
> generic (n: integer range 0 to 1024 := 2);
> port (clk, reset : in std_logic;
> load: in std_logic;
> count: buffer std_logic_vector (n downto 0);
> zero : out std_logic);
> end component;
>
> component automat
> port (clk, reset : in std_logic;
> nr, wr, zero, start : in std_logic;
> load : out std_logic;
> drive, sel: out std_logic_vector (1 downto 0));
> end component;
>
> ----deklaracje sygnalów
>
> signal tload, tzero : std_logic;
> signal tenable, tdrive : std_logic_vector (1 downto 0);
> signal tcount : std_logic_vector (2 downto 0);
>
> BEGIN
>
> --- przytoczenie komponentów
>
> U1 : reg1 port map(data, data, clk, tenable(1), tdrive(1));
> U2 : reg1 port map(data, data, clk, tenable(0), tdrive(0));
> U3 : automat port map(clk, reset, nr, wr, tzero, start, tload, tdrive,
> tenable);
> U4 : licznik port map(clk, reset, tload, tcount, tzero);
>
>
> END ARCHITECTURE str;