Asembler ARM
Zbigniew Kulesza
Asembler ARM
Zbigniew Kulesza
Strony internetowe
http://www.heyrick.co.uk/assembler/
http://www.open-research.org.uk/AR
MuC/
http://www.cse.cuhk.edu.hk/~ceg240
0/tutorial/ARM_Programming.pdf
Przesunięcia I
Arytmetyczne w lewo
MOV R1, #12
MOV R0, R1, LSL#2
•
On exit, R0 is 48
Logiczne w prawo
Rx, LSR #n lub
Rx, LSR Rn
Przesunięcia II
Arytmetyczne w lewo
Rx, ASR #n lub
Rx, ASR Rn
W prawo
Rx, ROR #n lub
Rx, ROR Rn
Skoki I
OPT 1
ADR R1, #&70
LDR R0, [R1]
CMP #0
BEQ Zero
STR R0, [R1, #2]
.Zero
MOV PC, R14
Skoki II
OPT 1
ADR R1, #&70
LDR R0, [R1]
CMP R0, #0
STRNE R0, [R1, #2]
MOV PC, R14
Skok z linkiem
.load_new_format
BL switch_screen_mode
BL get_screen_info
BL load_palette
.new_loop
MOV R1, R5
BL read_byte
CMP R0, #255
BLEQ read_loop
STRB R0, [R2, #1]!
ADC
ADC<suffix> <dest>, <op 1>, <op 2>
dest = op_1 + op_2 + carry
Dodawanie 2 liczb 128-bitowych
ADDS R0, R4, R8 ; Add low words
ADCS R1, R5, R9 ; Add next word, with carry
ADCS R2, R6, R10 ; Add third word, with carry
ADCS R3, R7, R11 ; Add high word, with carry
128 bit result: Registers 0, 1, 2, and 3
128 bit first: Registers 4, 5, 6, and 7
128 bit second: Registers 8, 9, 10, and 11.
ADD
ADD<suffix> <dest>, <op 1>, <op
2>
dest = op_1 + op_2
ADD R0, R1, R2 ; R0 = R1 + R2
ADD R0, R1, #256 ; R0 = R1 + 256
ADD R0, R2, R3,LSL#1 ; R0 = R2 +
(R3<<1)
AND
AND<suffix> <dest>, <op 1>, <op
2>
dest = op_1 AND op_2
AND R0, R0, #3
R0 = Keep bits zero and one of R0,
discard the rest.
BIC
BIC<suffix> <dest>, <op 1>, <op
2>
dest = op_1 AND (!op_2)
BIC R0, R0, #%1011
Clear bits zero, one, and three in R0.
Leave the remaining bits alone.
EOR
EOR<suffix> <dest>, <op 1>, <op
2>
dest = op_1 EOR op_2
EOR R0, R0, #3
Invert bits zero and one in R0
MOV
MOV<suffix> <dest>, <op 1>
dest = op_1
MOV R0, R0
R0 = R0... NOP instruction
MOV R0, R0, LSL#3 ;
R0 = R0 * 8
MOV PC, R14
Exit to caller
MVN
MVN<suffix> <dest>, <op 1>
dest = !op_1
MVN R0, #4
R0 = -5
MVN R0, #0
R0 = -1
ORR
ORR<suffix> <dest>, <op 1>, <op
2>
dest = op_1 OR op_2
ORR R0, R0, #3
Set bits zero and one in R0
RSB
RSB<suffix> <dest>, <op 1>, <op 2>
dest = op_2 - op_1
RSB R0, R1, R2
R0 = R2 - R1
RSB R0, R1, #256
R0 = 256 - R1
RSB R0, R2, R3,LSL#1
R0 = (R3 << 1) - R2
RSC
RSC<suffix> <dest>, <op 1>, <op
2>
dest = op_2 - op_1 - !carry
SBC
SBC<suffix> <dest>, <op 1>, <op
2>
dest = op_1 - op_2 - !carry
SUB
SUB<suffix> <dest>, <op 1>, <op 2>
dest = op_1 - op_2
SUB R0, R1, R2
R0 = R1 - R2
SUB R0, R1, #256
R0 = R1 - 256
SUB R0, R2, R3,LSL#1
R0 = R2 - (R3 << 1)
SWP
SWP<suffix> <dest>, <op 1>, [<op
2>]
Load a word from memory, address
pointed to by operand two, and put that
word in the destination register.
Store the contents of register operand
one to that same address.
MLA : Multiplication with
Accumulate
MLA<suffix> <dest>, <op 1>, <op
2>, <op 3>
dest = (op_1 * op_2) + op_3
MUL : Multiplication
MUL<suffix> <dest>, <op 1>, <op
2>
dest = op_1 * op_2
CMN : Compare Negative
CMN<suffix> <op 1>, <op 2>
status = op_1 - (- op_2)
CMN R0, #1
Compare R0 with -1
CMP : Compare
CMP<suffix> <op 1>, <op 2>
status = op_1 - op_2
TEQ : Test Equivalence
TEQ<suffix> <op 1>, <op 2>
Status = op_1 EOR op_2
TST : Test bits
TST<suffix> <op 1>, <op 2>
Status = op_1 AND op_2
TST R0, #%1
Test if bit zero is set in R0
STR and LDR I
Single Data Transfer
LDR R0, address
STR R0, address
LDRB R0, address
STRB R0, address
STR and LDR II
Single Data Transfer
STR R0, [Rbase]
Store R0 at Rbase.
STR R0, [Rbase, Rindex]
Store R0 at Rbase + Rindex.
STR R0, [Rbase, #index]
Store R0 at Rbase + index. Index is an immediate value.
STR R0, [R1, #16]
would load R0 from R1+16.
STR R0, [Rbase, Rindex]!
Store R0 at Rbase + Rindex, & write back new address
to Rbase.
STR and LDR III
Single Data Transfer
STR R0, [Rbase, #index]!
Store R0 at Rbase + index, & write back new
address to Rbase.
STR R0, [Rbase], Rindex
Store R0 at Rbase, & write back Rbase + Rindex to
Rbase.
STR R0, [Rbase, Rindex, LSL #2]
will store R0 at the address Rbase + (Rindex * 4)
STR R0, place
Will generate a PC-relative offset to 'place', and
store R0 there.
STM and LDM I
Multiple Data Transfer
xxM type cond base write-back, {register list}
'xx' is LD to load, or ST to store.
'type' is (stack and other):
LDMED LDMIB Pre-incremental load
LDMFD LDMIA Post-incremental load
LDMEA LDMDB Pre-decremental load
LDMFA LDMDA Post-decremental load
STMFA STMIB Pre-incremental store
STMEA STMIA Post-incremental store
STMFD STMDB Pre-decremental store
STMED STMDA Post-decremental store
STM and LDM II
Multiple Data Transfer
STMFD R13!, {R0, R1}
LDMFD R13!, {R1, R0}
STMFD R13!, {R0-R12, R14}
...
LDMFD R13!, {R0-R12, PC}
STMFD R13!, {R0-R12, R14}
...
LDMFD R13!, {R0-R12, PC}^