Macintosh Quadra 700

Developer Note

Developer Note

Developer Technical Publications

Apple Computer, Inc. 1991

PPLE

OMPUTER

, I

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Macintosh Quadra 700 Developer Note

Comparison with the Macintosh Quadra 900 computer

/ 19

2 The Expansion Interface / 21

Expansion slots / 22

NuBus slots / 23
Processor-direct slot / 25

PDS card specifications / 25
PDS signal load/drive limits / 30
PDS card design considerations / 33
Timing considerations / 34
Macintosh Quadra 700 Direct Slot interrupt
handling / 34

3 ROM Features / 37

ROM support for the MC68040 / 38

Support for built-in FPU / 38
Support for built-in MMU / 39
Gestalt and SysEnvirons values / 39
Support for new CopyBack cache mode / 40

Cache management by the ROM / 40
Cache management by applications / 41

New exception handlers / 42

ROM support for the video hardware / 42
ROM support for new ICs / 43

Support for Sonic Ethernet controller / 43
Support for SCSI controller / 43
Support for Memory Control Unit / 43
Support for custom sound ICs / 44

ROM software enhancements / 44

Support for RAM disk / 44
Support for virtual memory / 45
Enhanced DebugUtil routine / 45
Enhancements to QuickDraw / 45
Enhanced BlockMove routine / 46

ROM memory map / 46

Figures and Tables

Macintosh Quadra 700 Hardware / 1

Figure 1-1 Block diagram of the Macintosh Quadra 700

computer / 4

Figure 1-2 Simplified I/O address map for the

Macintosh Quadra 700 computer / 9

Figure 1-3 Simplified NuBus address map for the

Macintosh Quadra 700 computer / 10

Figure 1-4 View of the Macintosh Quadra 700 case / 14
Figure 1-5 Front and back views of the Macintosh

Quadra 700 computer / 15

Table 1-1 Display monitors and pixel depths for

different amounts of VRAM / 12

Table 1-2 Pinouts for internal and external SCSI

connectors / 17

Table 1-3 Pinout for floppy disk internal connector / 18
Table 1-4 Comparison of features on Macintosh Quadra

900 and Macintosh Quadra 700 computers /
19

The Expansion Interface / 21

Figure 2-1 Arrangement of the expansion slots in the

Macintosh IIci and the Macintosh Quadra 700
computers / 21

Figure 2-2 Dimensions of the PDS card / 26

Table 2-1 NuBus ’90 signals on the Macintosh Quadra

700 NuBus connector / 24

Table 2-2 Pinouts of the PDS connector / 27
Table 2-3 Non-microprocessor signals on the PDS

connector / 30

Table 2-4 Restricted microprocessor signals on the PDS

connector / 30

Table 2-5 68040 Direct Slot signals, loading or driving

limits / 31

Macintosh Quadra 700 Developer Note

Table 2-6 VIA2 interrupt lines / 34
Table 2-7 Interrupt mapping / 35

ROM Features / 37

Figure 3-1 ROM memory maps / 47

Preface

vii

Preface

About this note

This developer note describes the Macintosh Quadra 700 computer, a
powerful, new member of the Macintosh Quadra family of
computers. Using an MC68040 microprocessor and a compact,
vertical case, the Macintosh Quadra 700 delivers high performance in
a small package.

This developer note has three chapters. Chapter 1, “Macintosh
Quadra 700 Hardware,” describes the main features and emphasizes
the circuitry and the case design of the machine. Chapter 2, “The
Expansion Interface,” describes the expansion capabilities of the
machine. Chapter 3, “ROM Features,” describes the new features of
the ROM software.

It is assumed that hardware and software developers are already
familiar with both the functionality and programming requirements
of Macintosh computers. If you are unfamiliar with the Macintosh or
would simply like more technical information on the hardware, you
may want to obtain copies of related technical manuals. For
information on how to obtain these manuals, see the following
section.

viii

Macintosh Quadra 700 Developer Note

For more information

To supplement the information in this document, hardware and/or
software developers might wish to obtain related documentation
such as the Guide to the Macintosh Family Hardware, second edition;
Designing Cards and Drivers for the Macintosh Family, second edition;
and Inside Macintosh, Volumes I through VI. Copies of these technical
manuals are available through APDA

(Apple Programmers and

Developers Association).

Chapter 3, “ROM Features,” refers to Macintosh Technical Notes 261
and 282. Macintosh Technical Notes are also available through
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Preface

You may also wish to refer to the NuBus specification, IEEE Standard
for a Simple 32-bit Backplane Bus: NuBus, IEEE Std. 1196-1987, and to the
NuBus ’90 proposal, IEEE Standard for a Simple 32-bit Backplane Bus:
NuBus, IEEE Std. R1196-R-1990. You can obtain those documents by
mail from IEEE Service Center, 445 Hoes Lane, Piscataway, NJ 08854,
or telephone 201-981-0060.

Chapter 1 Macintosh Quadra 700

Hardware

This chapter describes the main features of the
Macintosh Quadra 700 computer, with emphasis on
new circuitry features and case design.

Macintosh Quadra 700 Developer Note

Introduction

The Macintosh Quadra 700 computer is a high-performance member
of the new Macintosh Quadra family of computers. It provides many
of the same functions as the Macintosh Quadra 900 computer but has
a different case design and a reduced feature set. A brief comparison
of the two machines is provided later in this chapter. For more
information on the Macintosh Quadra 900 computer, see the
Macintosh Quadra 900 Developer Note.

The Macintosh Quadra 700 includes several advanced features that
provide improved performance over that of members of the
Macintosh II computer family. Foremost of those features are the
Motorola MC68040 microprocessor and built-in video display
hardware. The MC68040 has several built-in features, including data
and instruction caches, a memory management unit (MMU), and a
floating-point unit (FPU). The computer’s built-in video hardware
provides 24-bit color and performance approaching that of the
Macintosh Display Card 8•24GC.

The Macintosh Quadra 700 computer’s case is the same size as that of
the Macintosh IIci, but it normally stands vertically to occupy a
minimum of desk space when used with a large monitor.

To enhance the overall capabilities of the Macintosh Quadra 700,
expansion opportunities are provided through two NuBus™ slots
and one processor-direct slot (PDS). Chapter 2, “The Expansion
Interface,” provides a detailed discussion of the Macintosh Quadra
700 computer’s expansion interface.

Summary of major features

The hardware features of the Macintosh Quadra 700 computer
include

•

a Motorola MC68040 microprocessor running at 25 MHz

•

a case designed to stand vertically on a desk

•

1 MB ROM soldered down; 1 MB SIMM (Single Inline Memory
Module) socket
for expansion

Chapter 1 Macintosh Quadra 700 Hardware

•

two banks of dynamic RAM with 4 MB in bank 1 and 0, 4, or
16 MB in bank 2

•

built-in video hardware with direct-access frame buffer and
separate video RAM

•

an improved SCSI (Small Computer System Interface) interface for
faster SCSI devices

•

built-in support for Ethernet by way of Apple

AUI (AAUI)

•

an Apple SuperDrive high-density floppy disk drive with 1.44 MB
capacity

•

two NuBus expansion slots with NuBus ’90 features

•

a processor-direct slot for lhigh-performance hardware expansion

•

sound input and output capabilities like those of the
Macintosh IIsi

Design architecture

The circuitry of the Macintosh Quadra 700 computer has many new
features along with older features that it shares with the
Macintosh IIci and Macintosh IIsi computers. This section describes
the circuit design of the Macintosh Quadra 700, with emphasis on the
custom integrated circuits that implement its new features.

Figure 1-1 is a simplified block diagram of the Macintosh Quadra 700
computer, showing the major hardware components and the address
and data buses. The major features shown on the block diagram are
the MC68040 microprocessor, the custom ICs, the built-in video
hardware, and the expansion connectors (processor-direct slot and
NuBus).

Macintosh Quadra 700 Developer Note

There are three main buses in the Macintosh Quadra 700 computer:
the system bus, the I/O bus, and NuBus. The system bus connects
directly to the pins of the MC68040 microprocessor and runs at the
processor’s clock rate, 25 MHz. Four controller ICs are connected to
the system bus: the MCU (Memory Control Unit), the custom
memory controller; YANCC, the NuBus controller; DAFB, the
frame-buffer controller; and the
SCSI controller.

The I/O bus in the Macintosh Quadra 700 computer is similar to the
I/O bus in the Macintosh IIfx computer. The I/O bus in the
Macintosh Quadra 700 computer runs at a clock rate of 15.6672 MHz.
The controller ICs that are connected to the I/O bus include the new
Enhanced ASC (Apple Sound Chip) and Sonic custom ICs as well as
ICs shared with older models.

The NuBus, the industry-standard expansion bus used in all
Macintosh II–family computers, runs at a clock rate of 10 MHz. The
NuBus in the Macintosh Quadra 700 computer includes several
features of NuBus ’90, including a clock signal at 20 MHz, twice the
normal rate. NuBus ’90 is the 1990 proposal for revision of the IEEE
standard for the NuBus (IEEE Std. R1196-R-1990). For more
information about NuBus, see Chapter 2,
“The Expansion Interface.”

Chapter 1 Macintosh Quadra 700 Hardware

•

Figure 1-1

Block diagram of the Macintosh Quadra 700

computer

Macintosh Quadra 700 Developer Note

Drivers

and

receivers

Port A (modem)

Port B (printer)

Channel A

Channel B

Internal floppy disk

connector

Sporty

custom amp.

Video

port

VIA1

Serial

ports

Internal
speaker

Apple Desktop

Bus ports

Internal hard
disk connector

Enhanced

ASC

DFAC

sound input

IOA0–11

IOA12–9

A2–1

IOD31–24

D31–24

Processor-

direct slot

NuBus

connectors

GI ADB

ADB

transceiver

RTC

Ethernet

AAUI

Sonic

Ethernet

controller

VIA2

IOA12–9

Left channel

Right channel

Sound out
jack

Mic (sound
in jack)

IOA31–0

IOD31–0

Bidirectional

bus

transceiver

I/O bus

A31–0

External
SCSI port

SCSI

Bidirectional

bus

transceiver

Relayer

custom

control

adapter

D31–0

DAFB
Farme
buffer

controller

Memory

Control

Unit

RAM
4 MB

System bus

Address bus

A31–0

Data bus

D31–0

0.5 MB SIMMs

VRAM

SIMM

0.5 MB

VRAM

Soldered

0.5 MB

1-4 MB SIMM

ROM

1 MB

JDB

custom

data bus

adapter

BA7–4

A31–0

D31–0

BD31–0

A22–2

D31–0

A31–0

D31–0

YANCC

NuBus

controller

CPU

MC68040

Bidirectional

bus

transceiver

0.5 MB SIMMs

RAM

0–16 MB

(4 SIMMs)

CLUT/DAC

SCC

Audio

DAC

SWIM

Chapter 1 Macintosh Quadra 700 Hardware

MC68040 microprocessor

The Macintosh Quadra 700 computer uses the MC68040
microprocessor. The MC68040 is the most powerful member of the
68000 family, with performance much faster than that of an MC68030
with the same clock speed. While the MC68040 is upwardly
compatible with application software written for the MC68020 and
MC68030, it also has many new features that contribute to its
increased processing power.

The new features of the MC68040 include

•

a redesigned and optimized integer unit

•

a built-in floating-point unit (FPU)

•

built-in memory management units (MMUs), one for instructions
and one for data

•

built-in instruction and data caches, 4 KB each

The MC68040 is different in many ways from the MC68020 and
MC68030. For example, the MC68040 microprocessor’s built-in
floating-point unit is not the same as the FPU in the MC68881;
similarly, the built-in MMU is not the same as the MMU in the
MC68851 or the MC68030. Also, the instruction and data caches in the
MC68040 use a new mode called CopyBack mode. For information
about these differences and the way they are reflected in the new
ROM software developed for the Macintosh Quadra 700, see
Chapter 3,
“ROM Features.”

♦

Note: The MC68040 has another new feature called cache
snooping. That feature is not used in the Macintosh Quadra 700
computer and is not supported by the software. Devices that
transfer data on the system bus, such as PDS bus masters, must
drive the snoop control pins to indicate no snooping.

Macintosh Quadra 700 Developer Note

Custom ICs

The Macintosh Quadra 700 computer incorporates many VLSI (very-
large scale integration) ICs. Some of those ICs, such as the Motorola
MC68040, are industry-standard designs, while others are Apple
custom ICs. Of the Apple custom ICs, some are also used in earlier
Macintosh computers; others are newly designed for the Macintosh
Quadra 700 computer. The new Apple custom ICs are described in
the sections that follow.

Chapter 1 Macintosh Quadra 700 Hardware

The Macintosh Quadra 700 computer shares three custom ICs with
earlier Macintosh models. Those ICs, which are not described in this
note, are

•

CLUT/DAC (color look-up table and digital-to-analog converter)
IC developed by Apple and used in the Macintosh Display Card
4•8, 8•24, and 8•24GC

•

DFAC (Digitally Filtered Audio Chip), the sound input and filter
IC first used in the Macintosh LC

•

SWIM (Super Woz Integrated Machine), the IC that supports the
SuperDrive high-density floppy disk drive

The Macintosh Quadra 700 computer uses several new Apple custom
ICs. Those ICs are listed here and described in the following sections.

•

JDB (Junction Data Bus), one of two ICs making up the I/O
Adapter, connecting the data signals from the system bus and the
I/O bus

•

Relayer, one of two ICs making up the I/O Adapter, controlling
the bus buffers and providing bus arbitration logic

•

MCU (Memory Control Unit), a custom IC that connects to the
system bus and controls regular and burst-mode data transfers to
and from the main RAM and ROM

•

YANCC (Yet Another NuBus Controller Chip), a custom IC that
controls the
NuBus interface

•

DAFB (Direct Access Frame Buffer), an IC that connects directly to
the system bus and controls the video RAM (frame buffer)

•

Enhanced ASC (Apple Sound Chip), a custom IC that replaces the
Apple Sound Chip

•

Sporty, a custom IC that provides sound output amplification
functions

The Macintosh Quadra 700 computer uses several other ICs that are
not Apple designs. Those ICs, which are not described in this note,
include

•

the SCSI interface IC, the NCR 53C96

•

Sonic, the DP83932 Ethernet controller IC made by National
Semiconductor

Macintosh Quadra 700 Developer Note

•

two VIAs (Versatile Interface Adapters) like the ones in earlier
members of the Macintosh II family

I/O bus adapter ICs: JDB and Relayer

The I/O bus enables the Macintosh Quadra 700 computer to use the
same I/O device controllers used in previous Macintosh computers.
The I/O bus clock runs at 15.6672 MHz and is completely
asynchronous to the system bus clock.

The I/O bus adapter is made up of two ICs named JDB (Junction Data
Bus) and Relayer, as shown in the block diagram in Figure 1-1. Two
ICs are used because of the high pin count required.

The functions of the JDB IC include

•

controlling the data path (dynamic bus sizing and data byte lane
routing)

•

synchronizing and distributing the reset signals

The functions of the Relayer IC include

•

generating chip select and DSACK signals for devices on the I/O
bus

•

converting timing signals between the system bus and the I/O bus

•

arbitrating between the system bus and the I/O bus

•

acting as watchdog for bus activity and timeout

•

controlling the address-bus transceiver ICs

•

generating the clock signal for the VIA ICs

The ICs making up the I/O bus adapter contain no programmable
registers and do not require support from the system software.

Memory Control Unit

The MCU connects to the system bus and provides control and
timing signals for ROM and RAM. The MCU supports all types of
MC68040 memory access, including burst modes.

Chapter 1 Macintosh Quadra 700 Hardware

ROM control

The MCU controls the Macintosh Quadra 700 1 MB ROM, which
consists of two 4-Mbit ROMs (each ROM is a 256K x 16-bit, 150-ns
device). A ROM SIMM socket is available for future expansion;
however, when a ROM SIMM is installed in this socket, the on-board
ROM will be automatically disabled.

When the computer is reset, the MCU maps ROM addresses into
memory beginning at address $0000 0000 and disables the system
RAM. As soon as the ROM code addresses the normal ROM space
($4000 0000), the MCU automatically remaps the ROM to its normal
addresses and restores RAM addressing starting at $0000 0000.

RAM control

The MCU controls two banks of dynamic RAM. The first bank
contains 4 MB soldered to the board. The second bank can accept four
standard 30-pin SIMMs. Like the expansion RAM for the
Macintosh IIci, the RAM devices must have fast page mode, and
access time must be 80 ns or less. Acceptable SIMM sizes are 1 MB
and 4 MB, and all four SIMMs must contain the same amount of
RAM. The amount of added RAM can be 4 MB or 16 MB, giving the
computer possible memory sizes of 4 MB, 8 MB, and 20 MB.

The MCU contains registers that the system software uses to set the
starting address of each bank of memory. At startup time, the system
software determines the sizes of the banks and assigns the bank
starting addresses so that the banks occupy contiguous memory
spaces.

SCSI controller IC

In the Macintosh Quadra 700 computer, the SCSI bus is controlled by
an NCR 53C96 integrated circuit. The DAFB generates the timing and
control signals to interface the 53C96 to the system bus; see the block
diagram in Figure 1-1.

The address map in Figure 1-2 shows the address ranges assigned to
the SCSI controller and the other ICs used for I/O in the Macintosh
Quadra 700 computer.

Macintosh Quadra 700 Developer Note

NuBus controller IC: YANCC

In the Macintosh Quadra 700 computer, three chips comprise the
interface between the system bus and the NuBus: the YANCC (Yet
Another NuBus Controller Chip) IC and two
16-bit transceiver ICs. The transceiver ICs are the same type as
thosein the Macintosh IIci.

The YANCC IC converts certain system bus cycles to NuBus cycles
and certain NuBus cycles to system bus cycles. The features of the
YANCC IC include

•

support for all types of single data transfers in either direction

•

a buffer, one long word deep, for pending writes from the
MC68040 to the NuBus

•

support for block move transfers between NuBus masters and
main memory

•

support for pseudoblock transfers between the MC68040 and
NuBus slaves

•

support for some new functions defined in the NuBus ’90
specification

Unlike the NuBus controllers in previous Macintosh computers, the
YANCC IC generates an interrupt when there is an error involving
the write buffer. Software controls this interrupt by means of a
control and status register in the YANCC. See Figure 1-3 for the
simplified NuBus address map.

Chapter 1 Macintosh Quadra 700 Hardware

•

Figure 1-2

Simplified I/O address map for the Macintosh Quadra 700

computer

$5FFF FF

$5002 000

$5001 600

$5001 400

$5000 800

$5000 400

$5000 200

$5000 000

Orwell cont

$5000 A00

$5000 C0

$5000 E0

$5001 E0

$5002 800

$5004 000

$5400 000

Reserved

(repeated images

$5000 0000 – $500

Sound

VIA1

SCC

Ethern

Ethernet PRO

VIA1

$5000 F000

SCSI

$5000 F400

Reserved for

Reserved for A

SWIM

Reserved for

$5002 A0

YANCC cont

Reserved for A

Macintosh II I/O space–– not used in Macinto

$F100 00

$6000 0

$5000 0

$4000 00

$0000

I/O

ROM

RAM

NuBus standa

slot space

Reserve

NuBus

supers

space

Etherne

MCU controls

VIA2

Reserved for A

$F000

$FFFF FFFF

Macintosh Quadra 700 Developer Note

•

Figure 1-3

Simplified NuBus address map for the Macintosh

Quadra 700 computer

$FFFF FFF

$F100 0
$F000 0

$6000 0

$5000 0

$4000 0

$0000 0

Reserve

NuBus

super slo

space

256 MB/s

I/O

ROM

RAM

$FFFF FFF

Reserved for A

NuBus stand

slot space

NuBus slot
NuBus slot
NuBus slot

NuBus slot

$FF00 00
$FE00 00

$FD00 00

$FC00 00
$FB00 00
$FA00 000
$F900 00
$F800 00
$F700 00
$F600 00
$F500 00
$F400 00
$F300 00
$F200 00
$F100 00

Expansion slo
Expansion slo
Expansion slo
Expansion slo
Expansion slo
Expansion slo
Expansion slo
Expansion slo

Reserve

$F000 00

NuBus superslot

Processor-direc

NuBus superslo

Video slot sp

Expansion supers

$E000 00

$D000 00

$C000 00

$B000 00

$A000 000

$9000 00

$8000 00

$7000 00

$6000 00

Reserve

NuBus

superslot

space

Video slot sp

Chapter 1 Macintosh Quadra 700 Hardware

Video frame-buffer controller IC: DAFB

The built-in video hardware in the Macintosh Quadra 700 computer
provides high-performance graphics on all current Macintosh
monitors. The video hardware is built around a video frame buffer
controlled by the DAFB (Direct Access Frame Buffer) IC.

The video frame buffer comprises four banks of video RAM
(VRAM); the basic configuration has 512 KB of VRAM installed in
the first of the four banks. That configuration supports 8 bits per pixel
on 12-inch and 13-inch monitors and 4 bits per pixel on 15-inch and
21-inch monitors. The basic configuration also supports VGA
monitors and broadcast (NTSC and PAL) monitors, but without
Apple convolution.

Each of the other three banks has two slots for VRAM SIMMs. The
VRAM SIMMs hold 256 KB each and are the same as the VRAM
SIMMs used in the Macintosh LC and the Macintosh Display Card
4•8. By installing a pair of VRAM SIMMs in the second bank
(the first pair of slots), the user can expand the frame buffer to
support 24 bits per pixel on the 12-inch monitor and 8 bits per pixel
on NTSC and PAL monitors, using Apple convolution to reduce
flicker. By installing additional VRAM SIMMs into the third and
fourth banks, the user can expand the frame buffer to support 24 bits
per pixel for the 13-inch monitor and for NTSC and PAL monitors
without convolution. Table 1-1 shows the pixel depth in bits per
pixel (bpp) for different monitors as a function of the amount of
VRAM installed.

Macintosh Quadra 700 Developer Note

•

Table 1-1

Display monitors and pixel depths for different

amounts of VRAM

Display size

1 bank of VRAM

2 banks of VRAM 4 banks of VRAM

NTSC and PAL,

8 bpp

24 bpp

without convolution

NTSC and PAL,

n.a.

8 bpp

with convolution

12-inch landscape 8 bpp

24 bpp

13-inch landscape 8 bpp

8 bpp

24 bpp

15-inch portrait

4 bpp

8 bpp

Two-page landscape

4 bpp

8 bpp

bpp

The video hardware in the Macintosh Quadra 700 computer
provides graphics performance approaching that of the Macintosh
Display Card 8•24GC. The 8•24GC card is faster for certain graphics
operations, but not all applications benefit from the acceleration it
provides. Because the frame buffer in the Macintosh Quadra 700
computer is connected directly to the system bus, it works with the
MC68040 to provide high drawing speed for all applications, even
those that don’t use QuickDraw™.

The control registers in the DAFB IC and the frame-buffer VRAM are
mapped into the memory locations that were assigned to NuBus slot
$9 in earlier Macintosh models. See Figure 1-3 for a map of the
NuBus addresses in the Macintosh Quadra 700 computer.

Chapter 1 Macintosh Quadra 700 Hardware

Sound ICs: DFAC, Enhanced ASC, and Sporty

The Macintosh Quadra 700 computer uses a new sound system. Its
features are similar to the features of the sound interface in the
Macintosh LC and the Macintosh IIsi. The features of the Macintosh
Quadra 700 sound interface include

•

the ability to record monophonic sound from the microphone
input

•

the ability to play 8-bit sound files

Three Apple custom ICs plus a digital-to-analog converter provide
the sound interface

•

DFAC, which provides sound input and an antialiasing filter

•

Enhanced ASC, an updated version of the Apple Sound Chip

•

Sporty, a custom IC that replaces the two Sony sound ICs

•

External digital-to-analog converter (DAC)

The DFAC (Digitally Filtered Audio Chip) is an Apple custom IC that
is also used in the Macintosh LC. The DFAC IC includes the
antialiasing filter and analog-to-digital converter (ADC) for sound
input.

For sound output, the Sporty custom IC replaces the two Sony ICs
used in earlier models and, together with the external DAC, provides
better sound quality with less noise and distortion. Like the Sony ICs
it replaces, the Sporty IC contains digital attenuators and power
amplifiers.

Macintosh Quadra 700 Developer Note

Case and connectors

The following sections describe the features of the case, including the
power supply and the external connectors.

Vertical case

The Macintosh Quadra 700 computer has a new case the same size as
that of the Macintosh IIci but designed to stand vertically. The case
has sufficient room for one internal Apple SuperDrive floppy disk
drive and one 3.5inch hard disk drive. Figure 1-4 shows the
appearance of the Macintosh Quadra 700 case. The user can remove
the feet shown in the figure install the extra feet provided in the box
to use the case horizontally. Figure 1-5 shows front and back views
with the positions of the controls and connectors.

•

Figure 1-4

View of the Macintosh Quadra 700 case

Chapter 1 Macintosh Quadra 700 Hardware

•

Figure 1-5

Front and back views of the Macintosh Quadra

700 computer

Front vi

Programme

buttons

Power o

indicato

Floppy disk d

out

NuBus port $E

NuBus port

Sound Ou

Mic In

ADB

Modem

Video

Serial po

AAUI

(FriendlyN

SCS

ADB

Powe

switch

Disk activ

indicator

Rese

Back vi

Power supply

The power supply in the Macintosh Quadra 700 computer is the
same as that in the Macintosh IIci. The power supply adapts
automatically to the AC voltage that is applied. The localization
package for the computer will include the appropriate power cord for
the destination country.

Macintosh Quadra 700 Developer Note

Programmer’s buttons

Like other models in the Macintosh II family, the Macintosh Quadra
700 computer has two pushbuttons, the reset button and the NMI
(nonmaskable interrupt) button. The buttons are recessed into the
front of the case to prevent their being pressed accidentally.

Microphone and Mic In connector

The Macintosh Quadra 700 computer has a Mic In connector in the
back, and a microphone is included with the computer. The
microphone is the same as the one provided with the Macintosh IIsi
and the Macintosh LC.

♦

Warning

Do not plug any device other than the Macintosh
microphone into the Mic In connector on the
Macintosh Quadra 700 computer. That connector
includes +8 volts on one of its pins. Plugging a device
such as a standard microphone, headphone, or
speaker into the Mic In connector could cause damage
to the device.

♦

The Macintosh Quadra 700 computer comes with an audio-cable
adapter like the one with the Macintosh IIsi and Macintosh LC
computers. The adapter is intended for users who wish to use the
computer to sample line-level devices such as home stereo systems.
The adapter mixes the two line-level signals to a single
(monophonic) audio signal that is fed to the Mic In connector.

♦

Note: Even though the audio adapter has two Line In connectors,
it mixes the stereo channels into a single monophonic signal;
stereo information is lost. The adapter has two connectors for the
user’s convenience and so that an external mixer is not
needed when connecting the computer to the most common type
of consumer
audio equipment.

Chapter 1 Macintosh Quadra 700 Hardware

Sound Out connector and speaker

Like the models in the Macintosh II family, the Macintosh Quadra
700 computer has an internal speaker. The Sound Out connector on
the Macintosh Quadra 700 computer is similar to the one on the
Macintosh II and has the same electrical characteristics.

Macintosh Quadra 700 Developer Note

SCSI connectors

The Macintosh Quadra 700 includes one internal 50-pin SCSI
connector and one external DB-25 SCSI connector. The external SCSI
connector is used for external peripheral devices such as hard disks,
scanners, and so on. The SCSI connectors are identical to those used
on Macintosh II–family computers. Table 1-2 shows the pinouts for
the internal and external SCSI connectors.

♦

Note: SCSI devices designed for external use should be terminated
if they are the last device on the chain. SCSI devices designed for
internal use should also be terminated.

•

Table 1-2

Pinouts for internal and external SCSI connectors

Internal (50-pin)

External (25-pin)

Signal name

/REQ

/MSG

/C/D

/I/O

/RST

/ATN

/ACK

/BSY

/SEL

/DBP

/DB0

/DB1

/DB2

/DB3

/DB4

/DB5

/DB6

/DB7

TPWR

Chapter 1 Macintosh Quadra 700 Hardware

Pins 20, 22,24, 26, 28, 7, 9, 14, 16, 18,

GND

30, 34, and all odd pins

and 24

except pin 25 (30 total)

Macintosh Quadra 700 Developer Note

Floppy disk connector

A single SWIM chip controls the internal SuperDrive. A 20-pin
connector provides the signal interface between the SWIM chip and
the drive. Table 1-3 shows the pinout for the floppy disk connector.

•

Table 1-3

Pinout for floppy disk internal connector

Pin number

Signal name

Signal description

GND

Ground

PH0

Phase 0: state-control line

GND

Ground

PH1

Phase 1: state-control line

GND

Ground

PH2

Phase 2 :state-control line

GND

Ground

PH3

Phase 3: register write strobe

n.c.

Not connected

/WRREQ

Write data request

+5V

+5 V

SEL

Head select

+12V

+12 V

/ENBL

Drive enable

+12V

+12 V

Read data

+12V

+12 V

W R

Write data

+12V

+12 V

n.c.

Not connected

Chapter 1 Macintosh Quadra 700 Hardware

Ethernet connector

The Ethernet connector on the Macintosh Quadra 700 computer is
the Apple AUI (AAUI) connector, which accepts the AUI (thick)
Ethernet cable or a FriendlyNet adapter. There are different
FriendlyNet adapters for the other kinds of Ethernet standard cable:
the CheaperNet (thin) cable and the 10BaseT (twisted pair) cable.

Macintosh Quadra 700 Developer Note

Comparison with the Macintosh Quadra 900 computer

Table 1-4 compares the features of the Macintosh Quadra 700 and
Macintosh Quadra 900 computers. For detailed information on the
Macintosh Quadra 900 computer, refer to the Macintosh Quadra 900
Developer Note.

•

Table 1-4

Comparison of features on Macintosh Quadra 900 and

Macintosh
Quadra 700 computers

Feature

Macintosh Quadra 900

Macintosh Quadra 700

Memory

4 banks of DRAM (all on SIMMs)

2 banks of DRAM (1 bank soldered;

1 bank SIMMs)

SCSI

Dual SCSI controllers (1 internal

Single SCSI controller (for both

and 1 external); Room for 4

internal and external SCSI devices)

internal SCSI devices, including any

and room for one internal 3.5-inch

combination of 3.5-inch and

hard disk

5.25-inch devices

NuBus

5 slots, 19 W power per slot

2 slots, 15 W per slot (or a

(or two 25 W slots and three 15 W

total not to exceed 30 W);

slots; or a total not to exceed 95 W);

only standard size NuBus

both oversize and standard NuBus

cards allowed

PDS

O1 PDS slot (cards will also work

1 PDS slot (cards will also work

in Macintosh Quadra 700)

in Macintosh Quadra 900)

Floppy SWIM/IOP

SWIM

Serial ports

SCC/IOP

SCC

ADB

Same as Macintosh IIfx

Same as Macintosh IIci

Video

2 banks of VRAM soldered;

1 bank of VRAM soldered;

2 banks for expansion VRAM

3 banks for expansion VRAM

Chapter 2

The Expansion Interface

This chapter describes the NuBus and processor-direct
slot expansion capabilities of the Macintosh Quadra 700
computer.

Macintosh Quadra 700 Developer Note

Expansion slots

The Macintosh Quadra 700 computer has two NuBus slots and one
PDS (processor-direct slot). The next two sections give the
specifications for the two kinds of expansion slots.

Figure 2-1 shows how the expansion slots are arranged on the main
circuit boards of the Macintosh IIci and Macintosh Quadra 700
computers. Notice the differences in the arrangements of the slots in
the two computers. Also notice the alignment of the PDS slot with
NuBus slot $E in the Macintosh Quadra 700 computer.

•

Figure 2-1

Arrangement of the expansion slots in the

Macintosh IIci and the Macintosh Quadra 700 computers

$C $D $E

Macintosh IIci
main logic boar

PDS

CPU

68030

Macintosh Quadra 7
main logic board

$E $D

PDS

CPU

68040

NuBus sl

Top(when vertical)

I/O connect

Chapter 2 The Expansion Interface

NuBus slots

The Macintosh Quadra 700 computer has two NuBus slots. The
NuBus slots are similar
to those on the earlier modular Macintosh computers except that
they support
NuBus ’90 features.

NuBus ’90 is the 1990 proposal for revision of the IEEE standard for
the NuBus (IEEE Std. R1196-R-1990). The NuBus slots in the
Macintosh Quadra 700 computer provide the following new features
described in that proposal:

•

New signals /TM2, /CLK2X, and /CLK2XEN support block
transfers at double the standard rate. The Macintosh Quadra 700
computer allows double-rate block
transfers between NuBus cards but does not support double-rate
transfers to or from the main memory.

•

NuBus ’90 defines new signals SB0 and SB1 for a serial bus on the
formerly reserved pins A2 and C2. The serial-bus signals are bused
and terminated, but the main circuit board does not drive them.

•

NuBus ’90 defines new signals /CM0, /CM1, /CM2, and /CBUSY
to support a cache-coherency protocol. Pins on the NuBus
connector are assigned to those signals, but the Macintosh Quadra
700 system doesn’t support them.

Macintosh Quadra 700 Developer Note

Table 2-1 lists the new signals described in the proposal for NuBus
’90.

•

Table 2-1

NuBus ’90 signals on the Macintosh Quadra 700

NuBus connector

Pin number Signal name

Function

SB0

†

High-speed serial bus, defined in NuBus
’90 proposal.

/TM2

†

New transfer mode; requests double-speed
transfer.

/CM0

†

For cache-coherency operations.

B10

/CM1

†

For cache-coherency operations.

B11

/CM2

†

For cache-coherency operations.

B24

/CLK2X

Synchronizes double-speed block transfers.

B26

/CLK2XEN If not connected to other NuBus ’90

signals, enables /CLK2X driver.

B27

/CBUSY

†

Used with cache-coherency operations.

SB1

†

High-speed serial bus, defined in NuBus
’90 proposal.

†

These signals are not driven or monitored by circuits in the Macintosh Quadra 700

computer.

♦

Important

The eight lines that were connected to the –5.2-volt
supply in the original NuBus specification are now
used for new features. Many older NuBus cards
connect those eight lines together; the presence of
such a card in a Macintosh Quadra 700 computer will
disable the new features that use those lines. All other
features of both old and new cards will operate
normally.

♦

For a complete listing of the NuBus connector pin assignments (not
including the new NuBus ’90 signals) and a description of the signals, see
Chapter 5, “NuBus Card Electrical Design Guide,” in Designing Cards and
Drivers for the Macintosh Family.

Chapter 2 The Expansion Interface

Processor-direct slot

The processor-direct slot is located in line with NuBus slot $E and
uses the same opening in the back. The use of a PDS card precludes
the use of a NuBus card in slot $E.

For maximum performance, the processor-direct slot is connected
directly to the MC68040 microprocessor by way of the system bus. (For
a description of the system bus, see “Design Architecture” in Chapter
1.)

Possible applications for a PDS expansion card include cache
memory, a video frame buffer, a DMA-based I/O controller,
expansion memory, or even an additional
MC68040 microprocessor.

♦

Note: The ROM software in the Macintosh Quadra 700 computer
may not support those hypothetical PDS cards.

PDS card specifications

A PDS card for the Macintosh Quadra 700 computer has the same
dimensions as a NuBus card and can include a back-panel connector.

The connector for the PDS card is a 140-pin connector manufactured
by KEL Connectors, Incorporated. The connector on the main circuit
board is KEL part number 8817-140-170SH; the corresponding
connector on the PDS card is part number 8807-140-170LH.

Figure 2-2 shows the locations of both the PDS connector and the
NuBus connector on the PDS card. Normally, only the PDS
connector is present on a PDS card.

Macintosh Quadra 700 Developer Note

•

Figure 2-2

Dimensions of the PDS card

♦

THE LONG VERSION DIMENSION (322.30

(12.689)) IS THE APPLE PREFERRED MAXIMUM

BOARD LENGTH THAT MATCHES THE STANDARD

PANEL SIZE.

♦

THIS DIMENSION IS THE MAXIMUM LENGTH

POSSIBLE FOR NON INTERFERENCE WITH

INTERNAL COMPONENTS AND IS NOT A STANDARD

PANEL SIZE.

Chapter 2 The Expansion Interface

Table 2-2 lists the signals on the pins of the PDS connector. Most of
those signals are connected directly to pins on the MC68040
microprocessor. Table 2-3 defines the PDS signals that are not directly
connected to the microprocessor. Table 2-4 shows two PDS signals
that are connected to the microprocessor but that are not to be
connected to a microprocessor on a PDS card.

♦

Important

The signals on the PDS connector are connected
directly to the MC68040 with no buffers. Therefore,
the address, data, and AUX.CPUCLK lines on a PDS
card must present capacitive loads of not more than
40 pF. All other lines must present capacitive loads of
not more than 20 pF.

♦

•

Table 2-2

Pinouts of the PDS connector

Pin number Signal name

Pin number

Signal name

GND

+5V

GND

SIZ1

R/W

/TIP.CPU

A11

n.c.

A13

/TEA

A15

/DLE

GND

SC1

A18

/TRST

A19

/CIOUT

A21

GND

A23

/BR.CPU

A24

/BR.40SLOT

A26

/BB

A29

/LOCK

A31

/MEMRESET

D31

/RSTO

Macintosh Quadra 700 Developer Note

D29

+5V

D27

n.c.

(continued)

Chapter 2 The Expansion Interface

•

Table 2-2

Pinouts of the PDS connector

(continued)

Pin number Signal name

Pin number

Signal name

D25

/NMRQ6

D24

GND

D22

/IPL0

+5V

/IPL1

D19

/IPL2

D17

–12V

GND

D14

n.c.

D13

n.c.

D11

n.c.

+5V

AUX.CPUCLK

106

107

108

+5V

109

110

SIZ0

GND

111

+5V

112

/TBI

A10

113

/TA

A12

114

GND

A14

115

/TS

A16

116

SC0

A17

117

/MI

+5V

118

/MI.SLOT

A20

119

/BG.40SLOT

A22

120

/BG.CPU

GND

121

+5V

A25

122

TT0

A27

123

TT1

A28

124

GND

(continued)

Macintosh Quadra 700 Developer Note

•

Table 2-2

Pinouts of the PDS connector

(continued)

Pin number Signal name

Pin number

Signal name

A30

125

TLN0

D30

126

TLN1

D28

127

/ANALOGRESET

D26

128

TM0

GND

129

TM1

D23

130

TM2

D21

131

+5V

D20

132

/PDS.SLOT.E.EN

D18

133

+12V

D16

134

n.c.

100

D15

135

TCK

101

+5V

136

TMS

102

D12

137

n.c.

103

D10

138

n.c.

104

GND

139

n.c.

105

140

+5V

♦

Note: The AUX.CPUCLK line is terminated with a series resistor.
To reduce reflections on this line, all loads on the card should be
lumped.

Chapter 2 The Expansion Interface

•

Table 2-3

Non-microprocessor signals on the PDS

connector

Signal name

Direction*

Function

/ANALOGRESET O

Open-collector line; enables PDS to

drive system reset signal; used only for
testing

AUX.CPUCLK

Buffered version of main processor’s

bus clock

/BG.40SLOT

Bus grant for PDS card

/BR.40SLOT

Bus request for PDS card

/MEMRESET

Fast reset generated by JDB IC for
Memory Control Unit IC

/MI.SLOT

Memory inhibit from PDS card to

Memory Control Unit IC

/NMRQ6

NuBus slot $E interrupt; also
connected to NuBus slot $E

/PDS.SLOT.E.EN I

Notifies YANCC NuBus controller IC
that PDS card is installed and is using
memory space assigned to NuBus
slot $E

*I indicates input from PDS card to main logic board; O indicates output from the
main logic board to the PDS card.

•

Table 2-4

Restricted microprocessor signals on the PDS connector

Signal name

Direction*

Function

/IPL(0–2)

Interrupt priority lines from PAL; not
to be used as wire-OR lines; can be
monitored by PDS card

/TIP.CPU

From MC68040 on main circuit board;
not connected to any other part of
computer

*I indicates input to PDS card; O indicates output from PDS card.

Macintosh Quadra 700 Developer Note

PDS signal load/drive limits

Table 2-5 shows the load presented or drive available to each pin of a
Macintosh Quadra 700 PDS expansion card and indicates whether the
signals are inputs or outputs. Using the signal /BB (Bus Busy) as an
example, the column in Table 2-5 labeled “Load or drive” limits is
interpreted as follows.

/BB is shown presenting a load of 100

A/4 mA, 70 pF. This is the

maximum expected load that an expansion card must drive when
sending the /BB signal to the main logic board. The DC load is in the
format signal high/signal low. This means that the expansion card
must drive a load of up to 100

A when it drives /BB high and a load

of up to 4 mA when it drives /BB low. The AC load is given as 70 pF,
the maximum capacitance to ground presented by the main logic
board to AC signals from the expansion card.

/BB is shown presenting a drive of 40

A/.4 mA, 20 pF. This is the

maximum amount of drive from the main logic board that is
available to integrated circuits on the expansion card. /BB can drive
an expansion card DC load of up to 40

A in the high state or up to

.4 mA in the low state. The AC drive is given as 20 pF, the maximum
capacitance to ground that an expansion card may present to AC
signals on the /BB line.

•

Table 2-5

68040 Direct Slot signals, loading or driving limits

Signal name

Input/output

Load or drive limits

A0–A31

Input/output Load: 200

A/2 mA, 150 pF

Drive: 40

A/.4 mA, 40 pF

/ANALOGRESET Output

Drive: 40

A/.4 mA, 20 pF

AUX.CPUCLK

Output

Drive: 40

A/.4 mA, 40 pF

/BB

Input/output Load: 100

A/4 mA, 70 pF

Drive: 40

A/.4 mA, 20 pF

/BG.CPU

Output

Drive: 40

A/.4 mA, 20 pF

/BG.40SLOT

Output

Drive: 40

A/.4 mA, 20 pF

/BR.CPU

Input

Load: 100

A/4 mA, 40 pF

/BR.40SLOT

Input

Load: 100

A/4 mA, 40 pF

/CIOUT

Output

Drive: 40

A/.4 mA, 20 pF

Chapter 2 The Expansion Interface

D0–D31

Input/output Load: 200

A/2 mA, 120 pF

Drive: 40

A/.4 mA, 40 pF

/DLE

Input

Load: 100

A/4 mA, 25 pF

/IPL0–/IPL2

Output

Drive: 40

A/.4 mA, 20 pF

/LOCK

Input/output Load: 100

A/4 mA, 25 pF

Drive: 40

A/.4 mA, 20 pF

/MEMRESET

Output

Drive: 40

A/.4 mA, 20 pF

/MI

Input/output Load: 100

A/4 mA, 25 pF

Drive: 40

A/.4 mA, 40 pF

(continued)

•

Table 2-5

68040 Direct Slot signals, loading or driving limits

(continued)

Signal name

Input/output

Load or drive limits

/MI.SLOT

Input

Load: 100

A/4 mA, 20 pF

/NMRQ6

Input

Load: 100

A/4 mA, 40 pF

/PDS.SLOT.E.EN

Input

Load: 100

A/4 mA, 20 pF

/RSTO

Output

Drive: 40

A/.4 mA, 20 pF

R/W

Input/output Load: 100

A/4 mA, 100 pF

Drive: 40

A/.4 mA, 20 pF

SC0-SC1

Input/output Load: 100

A/4 mA, 40 pF

Drive: 40

A/.4 mA, 20 pF

SIZ0–SIZ1

Input/output Load: 100

A/4 mA, 90 pF

Drive: 40

A/.4 mA, 20 pF

/TA

Input/output Load: 100

A/4 mA, 100 pF

Drive: 40

A/.4 mA, 20 pF

/TBI

Input/output Load: 100

A/4 mA, 100 pF

Drive: 40

A/.4 mA, 20 pF

TCK

Input

Load: 100

A/4 mA, 25 pF

/TEA

Input/output Load: 100

A/4 mA, 100 pF

Drive: 40

A/.4 mA, 20 pF

/TIP.CPU

Output

Drive: 40

A/.4 mA, 20 pF

TLN0–TLN1

Output

Drive: 40

A/.4 mA, 20 pF

TM0–TM2

Output

Drive: 40

A/.4 mA, 20 pF

TMS

Input

Load: 100

A/4 mA, 25 pF

/TRST

Input

Load: 100

A/4 mA, 25 pF

/TS

Input/output Load: 100

A/4 mA, 90 pF

Drive: 40

A/.4 mA, 20 pF

Macintosh Quadra 700 Developer Note

TT0–TT1

Input/output Load: 100

A/4 mA, 90 pF

Drive: 40

A/.4 mA, 20 pF

♦

Note: Input denotes direction from PDS card to main logic board,
but not necessarily the processor. Output denotes direction from
main logic board, but not necessarily the processor, to the PDS
card.

PDS card design considerations

A PDS card can have memory locations in the upper part of the
RAM memory space or in the space assigned to NuBus slot $E. (See
the NuBus memory map in Figure 1-3 of
Chapter 1, “The Macintosh Quadra 700 Hardware.”) If the card uses
slot $E addresses, it must decode all addresses in both the slot space
and the superslot space, responding to any access to an unused
location with a /TEA (Transfer Error Acknowledge) signal on the
processor bus to indicate an illegal address.

A typical PDS card maps into the NuBus slot $E space and works
with the system software’s Slot Manager. Such a card must contain a
NuBus declaration ROM and must notify the NuBus controller that
it is using the NuBus space by asserting (pulling low) the signal
/PDS.SLOT.E.EN on the PDS connector.

A PDS card that asserts the /PDS.SLOT.E.EN signal must issue a /TA
(Transfer Acknowledge) or a /TEA in response to all accesses to the
$Exxx xxx and $FExx xxxx address space. (This action will keep the
machine from hanging, since there is no timeout timer for slot $E
when the /PDS.SLOT.E.EN signal is asserted.)

A PDS card functioning as bus master must drive all control signals
to a known state
when it requests the system bus. Snoop control bits, in particular,
must be driven to indicate no snoop.

Chapter 2 The Expansion Interface

By convention, all devices on the system bus, including a PDS card,
must drive tristate signals active for one-half of a clock cycle before
going tristate. For example, a PDS card functioning as the slave
should drive /TA high after the address space is decoded, then drive
it low for one clock cycle, and finally drive it high at the end of that
clock cycle. /TA should go tristate one-half clock cycle later. If you
follow these guidelines in your PDS card design, the control lines
will have cleaner edges, resulting in more reliable operation of your
card.

♦

Warning

A PDS expansion card for the Macintosh Quadra 700
computer must be designed to work with the
MC68040 microprocessor. PDS cards designed for
computers that use the MC68020 or the MC68030 will
not work in the Macintosh Quadra 700 computer.

♦

Macintosh Quadra 700 Developer Note

Timing considerations

The signal timing for the PDS connector depends on the clock speed
of the 68040 microprocessor. Developers of PDS expansion cards
should clearly indicate on the card the maximum clock speed of the
card.

The timing of a PDS card’s output signals must be equal to or better
than the
worst-case delay output timing of the 68040 microprocessor. Also,
input signals to
a PDS card cannot expect more setup time than is required for a
signal to set up on the 68040 microprocessor.

Macintosh Quadra 700 Direct Slot interrupt handling

The

interrupt-handling mechanism for the 68040 Direct Slot on the

Macintosh Quadra 700 is similar to the one used in the Macintosh II
family. The two NuBus interrupt signals (slot $E interrupt is shared by
the 68040 Direct Slot), the built-in video interrupt signal, and the
Ethernet controller interrupt signal are routed through an OR gate to
generate a signal
called /SLOTIRQ. This signal is connected to the CA1 input of VIA2,
the second VIA chip
on the logic board. This VIA generates a level 2 interrupt to the
MC68040. This VIA can
also generate an interrupt in response to SCSI requests, sound chip
requests, or
VIA timer requests.

All interrupts to the MC68040 are autovectored. When the MC68040
is executing a level x interrupt, it first sets the interrupt mask to level
x, so further interrupts at level x and below will be ignored. Once the
interrupt handler is executed and an RTE instruction is processed,
the interrupt mask is restored to the value it had before the
interrupt.

The first-level interrupt dispatcher determines which hardware
device—SCSI, sound chip, real-time clock, or expansion slot—is
requesting the interrupt and dispatches code to the appropriate
interrupt handler. If the interrupt generated by the VIA is a slot
interrupt, the software polls the second VIA, bits PA0 through PA6,
to determine which slot generated the interrupt. Table 2-6
summarizes the interrupt lines for VIA2.

Chapter 2 The Expansion Interface

•

Table 2-6

VIA2 interrupt lines

Address

Description

PA0

Ethernet IRQ

PA1

Not connected

PA2

Not connected

PA3

Not connected

PA4

Slot $D IRQ

PA5

Slot $E IRQ

PA6

Video IRQ

Once the software determines which pseudoslot generated the
interrupt, the Slot Manager software executes the interrupt handler
for that slot device. The handler for that device was installed at boot
time when the initialization software polled the possible slots and
identified the existence of a card in the slot by its ROM signature.

There is a delay between the assertion of a slot interrupt and the
actual execution of the interrupt handler. During this time, the
software polls the actual slot /IRQ signal. The recommended design
practice is to latch the slot /IRQ signal so that once it is asserted, the
interrupt handler software for the card has the responsibility of
clearing the interrupt. This ensures that the slot /IRQ signal is
asserted when polled and that the Slot Manager is dispatched
correctly.

In addition to the standard Macintosh II functions, the VIA1 includes
two new bits. The first is a software interrupt signal, and the second
is the A/UX interrupt enable signal. When the software interrupt bit
is set, an interrupt will be passed to the MC68040. When the A/UX
interrupt enable bit is set, the interrupt control PAL will remap the
interrupts. Table 2-7 shows the Macintosh and A/UX operating
system interrupts, where priority 0 is low, and priority 7 is high.

•

Table 2-7

Interrupt mapping

Interrupt

Macintosh A/UX

priority

interrupt

0
1

VIA1 Software

VIA2 (SCSI, sound, NuBus

VIA2 (SCSI, NuBus

slots, Ethernet, video)

slots, video)

Macintosh Quadra 700 Developer Note

Ethernet

SCC

Sound

VIA1

NMI/YANCC err

Chapter 3 ROM Features

This chapter describes the ROM software in the
Macintosh Quadra 700 computer, with emphasis on the
new features.

Macintosh Quadra 700 Developer Note

The Macintosh Quadra 700 computer uses a 1 MB ROM. The first
half of the ROM is an overpatch of the 512 KB ROM used in other
members of the Macintosh-II family. The second half of the ROM is
new software to support the new features of the Macintosh Quadra
700 computer. “ROM Memory Map” at the end of this chapter
describes the format of the ROM.

The Macintosh Quadra 700 ROM includes new code in several areas,
including

•

support for the MC68040, including FPU, MMU, and caches

•

support for video hardware

•

support for new custom ICs

•

new software enhancements

ROM support for the MC68040

The MC68040 microprocessor is different in many ways from the
MC68030 and earlier members of the 68000 family. The MC68040
incorporates a built-in floating-point unit (FPU), a built-in memory
management unit (MMU), caches for instructions and data, and
many other new features that contribute to its improved
performance. The ROM for the Macintosh Quadra 700 computer
incorporates the many changes required to take advantage of the new
features of the MC68040.

Support for built-in FPU

The ROM software for the Macintosh Quadra 700 computer includes
new code to support the differences between the FPU in the MC68040
and the MC68881 and MC68882 FPUs used with the MC68020 and
MC68030.

Chapter 3 ROM Features

The method of detecting an FPU that was used in earlier ROM
software does not work for the FPU in the MC68040, so the new ROM
uses a different method. Also, the floating-point software in the new
ROM incorporates several enhancements to the SANE routines,
including

Ω

SANE, which speeds up SANE calls made by way of A-

traps.

The FPU in the MC68040 does not handle all the instructions and
data types that the MC68881 and MC68882 handle, so the ROM
software includes new code to deal with those instructions and data
types. For example, the exception vector table has a new exception
vector to software that handles data types not supported by the FPU.

Macintosh Quadra 700 Developer Note

Support for built-in MMU

The MMU in the MC68040 is different in many ways from the
MC68851 used with the MC68020 and from the built-in MMU in the
MC68030. The registers and table-entry layouts are different; also, the
MC68040 does not support certain features of the MC68851 and the
MMU in the MC68030. The new ROM software generates the correct
tables and register values for either type of MMU.

♦

Note: The MMU opcodes on the MC68040 are different from those
on the MC68030. For example, both microprocessors have a PTEST
operation, but the PTEST opcode for the MC68030 generates an
unimplemented-instruction exception on the MC68040.

The MMU is set up to support only one ROM address space and one
I/O address space. Actually, only one address space for each is
necessary, and mapping one image of each address space reduces the
size of the MMU tables.

The Macintosh Quadra 700 computer and the Macintosh Quadra 900
computer are the first Macintosh models to combine an MMU with
built-in video using frame buffers in separate banks of VRAM. The
ROM software manages the address space for the video frame buffers
separately from main memory.

Gestalt and SysEnvirons values

Applications can determine in which Macintosh model they are
running in by using the Gestalt routine. Use the SysEnvirons routine
on models that don’t have the Gestalt routine. For the Macintosh
Quadra 700 computer, the machine type for Gestalt is 22; the
SysEnvirons machine type is 20. The Gestalt routine also returns
some other useful values:

•

In the processor field, env68040 = 5.

•

The gestaltFPUType selector returns gestalt68040FPU = 3.

•

The gestaltMMUType selector returns gestalt68040MMU = 4.

•

The gestaltProcessorType selector returns gestalt68040 = 5.

Chapter 3 ROM Features

Support for new CopyBack cache mode

The MC68040 microprocessor has two internal caches, one for
instructions and one for data. The caches perform the same function
as those on earlier processors, storing the contents of recently
addressed memory locations in anticipation that those contents will
soon be used again.

The data cache in the MC68040 microprocessor has a new mode
called the CopyBack mode. That mode is different from the
WriteThru mode used by the caches in the MC68020 and MC68030
microprocessors. The CopyBack mode improves the overall
performance because the processor can write to a memory location
several times before the data must be flushed from the cache.
Operating in the CopyBack mode can increase the processor’s
performance by up to 50 percent but also requires the operating
system to manage some types of data more carefully.

The difference between the WriteThru and CopyBack modes on the
MC68040 is the way they deal with data being written to memory. In
WriteThru mode, the MC68040 writes the data to main memory
immediately and also updates the cache. In CopyBack mode, the
MC68040 writes directly to the cache, and main memory is not
immediately updated. The cache then writes the data to main
memory when that portion of the data cache is selected for
replacement or when the data cache is flushed.

Cache management by the ROM

One consequence of the use of CopyBack mode is that main memory
does not always contain the latest data. One way that old data can
cause a problem is when an alternate bus master reads from memory
that is being cached by the main processor and that
has not been updated. To prevent this problem from arising, the
ROM software uses
only pages marked uncacheable when setting up communication
areas with alternate
bus masters.

Macintosh Quadra 700 Developer Note

Another way old data can cause a problem is when the
microprocessor fills its instruction cache from an area with old data.
To prevent that problem, the ROM software flushes the contents of
the data cache to main memory after writing data that consists of
instruction code. Specifically, the software flushes the data cache to
main memory after each of the following operations:

•

loading a resource into memory

•

moving a heap block

•

creating a jump table

♦

Note: The ROM software in the Macintosh Quadra 700 computer
invalidates the caches in the MC68040 microprocessor in the same
places that the older ROM software invalidated the caches in the
MC68020 and MC68030 microprocessors.

Cache management by applications

It has always been important to flush the caches on the MC68020 and
MC68030 before executing instructions that were recently written to
memory. On the MC68040, flushing only the instruction cache in this
situation is not sufficient. The instruction and data caches are
independent of each other, and there is a strong possibility that the
instruction cache will fill with old data from RAM while the new
data has not yet been written to RAM from the data cache.

To prevent this problem in your applications, it is vital that you use
one or more of the calls provided by the system software whenever
you write data that will be executed as instructions. You can use the
_FlushInstructionCache and _FlushDataCache calls, described in
Macintosh Technical Note 261, to flush the caches. Because the
purpose of the _FlushInstructionCache call is to maintain cache
coherency, its operation on the MC68040 is to flush both the
instruction cache and the data cache. Flushing both caches with one
call also avoids problems in situations where interrupts might occur
while the caches are being flushed individually.

Chapter 3 ROM Features

♦

Important

Flushing the cache at certain times is critically
important,
but it is also important not to flush the cache too
often. Unnecessary flushing of the cache impairs the
performance of the MC68040 microprocessor.

♦

New exception handlers

Unlike the previous processors in the 68000 family, the MC68040
handles exceptions by the method called instruction restart. The
processor recognizes exceptions at each instruction boundary in the
execute stage of the integer pipeline and forces later instructions that
have not yet reached the execute stage to be aborted. Also, the
MC68040 creates some new exception stack frames, including those
for its version of bus errors, which are called access errors.

Exception handlers, particularly bus error handlers, are affected by
those differences. The ROM software includes appropriate changes to
the universal startup code and modified bus error handlers for the
Slot Manager and the Memory Manager.

ROM support for the video hardware

The Macintosh Quadra 700 computer has built-in video hardware
with dedicated VRAM frame buffers controlled by a new custom IC
called DAFB. The ROM software includes a new video driver to
support the new hardware.

Because the MC68040 puts data on the data bus in a way that is
different from the way the MC68020 and MC68030 do, the software
on Apple’s older video display cards must be modified to function
correctly with the MC68040. The ROM software in the Macintosh
Quadra 700 computer patches the ROM software on the display cards
so that they operate normally. The affected cards are the Macintosh II
Video Card and early versions of Macintosh Display Cards 4•8 and
8•24.

Macintosh Quadra 700 Developer Note

The problem with the video cards occurs because the cards rely on a
feature of the MC68020 and MC68030 called byte smearing that is
absent from the MC68040. The Slot Manager and the Device Manager
have been patched to recognize those cards and substitute corrected
code for their primary initialization software and video driver.

♦

Note: Third-party accelerator cards that use the MC68040 will
encounter the byte-smearing problem when used with the older
display cards listed above. For more information, refer to
Macintosh Technical Note 282.

ROM support for new ICs

The ROM software includes new routines to support the following
new ICs:

•

Sonic IC (National DP83932) for built-in Ethernet

•

NCR 53C96 IC for SCSI ports

•

Memory Control Unit IC for memory addressing and control

•

Enhanced ASC, Sporty, and DFAC ICs for sound processing

Support for Sonic Ethernet controller

The ROM software includes a new driver to support the Sonic IC.
Developers can contact Apple Evangelism to obtain more
information about built-in Ethernet, FriendlyNet,
and Apple AUI.

Chapter 3 ROM Features

Support for SCSI controller

The ROM software supports the new SCSI bus design using the NCR
53C96. Because the same ROM code will be used in future models
that do not use that IC, the ROM software that supports the SCSI
Manager is a separate module addressed by a vector that is set up at
startup time.

Support for Memory Control Unit

Main RAM in the Macintosh Quadra 700 computer consists of two
banks that begin on
64 MB boundaries. At startup time, the ROM software determines
the amount of
RAM installed in each bank and stores the actual bank sizes in
registers in the Memory Control Unit IC. Using those bank sizes, the
Memory Control Unit IC decodes bus addresses so that the separate
physical banks of RAM occupy contiguous addresses
in logical memory space.

upport for custom sound ICs

The ROM software for the Macintosh Quadra 700 computer supports
the new Enhanced ASC, Sporty, and DFAC custom ICs. The new ICs
and software support the sound modes provided by the previous
Apple Sound Chip as well as a record mode for sound input.

ROM software enhancements

The ROM software includes the following enhancements:

•

support for a RAM disk

•

support for virtual memory (VM)

•

an enhanced DebugUtil routine

Macintosh Quadra 700 Developer Note

•

enhancements to QuickDraw

•

an enhanced BlockMove routine

Support for RAM disk

The ROM software includes the capability to create a RAM disk that
can then be used as the startup disk. The idea of a RAM disk was first
proposed for the Macintosh Portable as a way of saving power by
eliminating the need for continual disk activity. The RAM disk also
increases performance of programs that execute and fetch data from
the RAM disk, including the Macintosh Operating System.

In order for the RAM disk to work on a machine that uses an MMU,
the RAM disk must be supported by ROM software. The software
determines that the RAM disk is operating during warm starts and
makes sure that its contents are not corrupted during the
startup process.

The RAM disk driver works in concert with the MMU to protect the
contents of the RAM disk from runaway applications. Using the
MMU, the driver write-protects the memory pages that make up the
RAM disk. The driver can unprotect individual pages when it is
called upon to write data to disk, but the driver immediately protects
the pages again before it exits. By protecting the contents of the RAM
disk, the driver makes it possible for the user to restart the system
from the RAM disk even after a system crash or reset.

Support for virtual memory

Starting with the Macintosh IIci computer, ROM software has
provided some of the virtual memory routines to allow
programmers to manipulate the tables in the MMU. The ROM
software for the Macintosh Quadra 700 computer includes
modifications to those routines to support the MC68040, along with
some enhancements to provide write-protection capability for the
main memory.

Chapter 3 ROM Features

Specifically, the existing routines LockMemory,
LockMemoryContiguous, and UnlockMemory can change the
attributes of individual pages in the absence of VM.

The ability to set the attributes of individual pages in memory
becomes important with the advent of the large internal caches of
the MC68040 and the common use of alternate bus masters. For
example, when an area in memory is used as a communication
buffer between the main processor and an alternate bus master, that
area of memory must be marked uncacheable to maintain cache
coherency after writes from the alternate bus master. On earlier
machines that used the MC68020 and MC68030, it was acceptable to
turn off the entire cache whenever any pages needed to be
uncacheable, due to the small sizes of the caches on those processors
and the limited number of bus masters. On a machine with an
MC68040 and on-board bus masters, such a practice would result in
an unacceptable degradation of performance.

Enhanced DebugUtil routine

DebugUtil is a routine that provides debuggers with low-level
services that would otherwise require direct hardware manipulation
by the debugger. Putting that kind of hardware-dependent code into
the ROM relieves debuggers of some of the burden of supporting
different hardware platforms.

Enhancements to QuickDraw

Two new features of the Macintosh Quadra 700 computer provide
opportunities for optimization of QuickDraw operations. Those
features are the faster operation of the video frame buffer and a new
instruction in the MC68040.

The DAFB has different modes of operation of the frame buffer.
QuickDraw on the Macintosh Quadra 700 computer simply sets the
DAFB to its fastest mode of operation (per display and per bit depth)
and performs all drawing operations in that mode.

Macintosh Quadra 700 Developer Note

The MC68040 has a new instruction, MOVE16, that speeds the
unmodified copy operation. Even though this operation is not used
with clipping, depth conversion, colorizing, stretching, or shrinking,
it is used for many operations such as vertical scrolling, where it
provides a significant speedup.

♦

Warning

If you plan to use the MOVE16 instruction in code
you are writing, you should be aware that there are
limitations on its use. Refer to the latest MC68040
information from Motorola.

♦

Enhanced BlockMove routine

The BlockMove routine in the previous ROM software checks the
length of all requested transfers and chooses from MOVE.B,
MOVE.W, MOVE.L, and MOVEM.L instructions to move data from
place to place in memory. The addition of the MOVE16 instruction
in the MC68040 enables the new ROM software to provide further
optimization.

ROM memory map

The ROM software for the Macintosh Quadra 700 computer is
derived from the universal ROM used in the Macintosh IIci,
Macintosh IIfx, Macintosh IIsi, and Macintosh LC computers. It uses
the same patch file and supports all Macintosh models that use 32-bit
processors—MC68020 and MC68030 as well as MC68040.

The Macintosh Quadra 700 ROM is a 1 MB ROM device. Figure 3-1
shows the memory map for the Macintosh Quadra 700 ROM along
with the map for the earlier 512 KB ROM used in the Macintosh IIci,
Macintosh IIfx, Macintosh IIsi, and Macintosh LC.

Chapter 3 ROM Features

The first half of the ROM is an overpatch of the ROM used in the
Macintosh IIci computer and preserves as much of the original ROM
image as possible. The few changes include the startup diagnostics,
located at the end of the code section, and the declaration ROM,
which is always located at the highest addresses in the ROM.

The second half of the ROM contains the new code and resources
needed to support the Macintosh Quadra 700 computer. The
structure of the second half is similar to that of the first, with the
code starting at low addresses and growing toward higher addresses,
and the resources starting just below the declaration ROM and
growing downward toward lower addresses. Because the ROM
resources are stored in the form of a linked list, the resources in the
second half of the ROM are available to the resource initialization
code as simply a continuation of the original list of resources.

•

Figure 3-1

ROM memory maps

$00 00

$80 00

$100 00

ROM cod

Overpatch a

Free spa

ROM resour

Declaration R

ROM cod

Overpatch a

ROM resour

New ROM co

New ROM resou

Declaration R

Free spa

Macintosh IIci

Macintosh Quadra 70

PPLE

UBLISHING

YSTEM

This Apple manual was written,
edited, and composed on a desktop
publishing system using Apple
Macintosh computers and
Microsoft Word software. Proof and
final pages were created on Apple
LaserWriter printers. Line art was
created using MacDraw

® and

Adobe

Illustrator. PostScript

, the page-

description language for the
LaserWriter, was developed by Adobe
Systems Incorporated.

Text type and display type are Apple’s
corporate font, a condensed version of
ITC Garamond

. Bullets are ITC Zapf

Dingbats

. Some elements, such as

program listings, are set in Apple
Courier.

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