1/13

TDA7266D

May 2003

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

■

WIDE SUPPLY VOLTAGE RANGE (3.5 - 12V)

■

OUTPUT POWER
5+5W @THD = 10%, R

L

= 8

Ω

, V

CC

= 9.5V

■

SINGLE SUPPLY

■

MINIMUM EXTERNAL COMPONENTS

– NO SVR CAPACITOR

– NO BOOTSTRAP

– NO BOUCHEROT CELLS

– INTERNALLY FIXED GAIN

■

STAND-BY & MUTE FUNCTIONS

■

SHORT CIRCUIT PROTECTION

■

THERMAL OVERLOAD PROTECTION

DESCRIPTION

The TDA7266D is a dual bridge amplifier specially

designed for LCD TV/Monitor, PC Motherboard, TV
and Portable Audio applications.

PowerSO20 Slug Down

ORDERING NUMBER: TDA7266D

PRELIMINARY DATA

5W+5W DUAL BRIDGE AMPLIFIER

TEST AND APPLICATION CIRCUIT

2

5

7

Vref

ST-BY

JP1

9

IN1

C3 0.22

µ

F

VCC

15

6

D02AU1407

+

-

-

+

OUT1+

OUT1-

19

16

14

MUTE

8

IN2

C5 0.22

µ

F

+

-

-

+

OUT2+

OUT2-

20

13

S-GND

PW-GND

C1

470

µ

F

C2

100nF

C7

100nF

1

10

11

C4

10

µ

F

R1

47K

R2

47K

C6

1

µ

F

R3 10K

R4 10K

+5V

TECHNOLOGY BI20II

TDA7266D

2/13

ABSOLUTE MAXIMUM RATINGS

THERMAL DATA

Notes: 1. See Application note AN668, available on WEB FR4 with 15 via holes and ground layer.

PIN CONNECTION

Symbol

Parameter

Value

Unit

V

s

Supply Voltage

20

V

I

O

Output Peak Current (internally limited)

1.5

A

P

tot

Total Power Dissipation (T

amb

= 70°C

25

W

T

op

Operating Temperature

0 to 70

°C

T

stg,

T

j

Storage and Junction Temperature

-40 to 150

°C

Symbol

Parameter

Value

Unit

R

th j-case

Thermal Resistance Junction-case

2.1

°C/W

R

th j-amb

Thermal Resistance Junction-ambient (on recomended PCB) note1

15

°C/W

PW GND

ST BY

N.C.

N.C.

N.C.

V

CC

OUT1-

IN1

MUTE

OUT1+

PW GND

10

8

9

7

6

5

4

3

2

13

14

15

16

17

19

18

20

12

1

11

PW GND

D02AU1408

SGND

IN2-

OUT2-

V

CC

N.C.

N.C.

OUT2+

PW GND

3/13

TDA7266D

ELECTRICAL CHARACTERISTCS (Refer to test circuit) V

CC

= 9.5V, R

L

= 8

Ω

, f = 1KHz, T

amb

= 25°C unless

otherwise specified)

Symbol

Parameter

Test Condition

Min.

Typ.

Max.

Unit

V

CC

Supply Range

3.5

9.5

12

V

I

q

Total Quiescent Current

50

60

mA

V

OS

Output Offset Voltage

120

mV

P

O

Output Power

THD 10%

4.3

5

W

THD

Total Harmonic Distortion

P

O

= 1W

0.05

0.2

%

P

O

= 0.1W to 2W

f = 100Hz to 15KHz

1

%

SVR

Supply Voltage Rejection

f = 100Hz, VR =0.5V

40

56

dB

CT

Crosstalk

46

60

dB

A

MUTE

Mute Attenuation

60

80

dB

T

w

Thermal Threshold

150

°C

G

V

Closed Loop Voltage Gain

25

26

27

dB

∆

G

V

Voltage Gain Matching

0.5

dB

R

i

Input Resistance

25

30

K

Ω

VT

MUTE

Mute Threshold

for V

CC

> 6.4V; Vo = -30dB

2.3

2.9

4.1

V

for V

CC

< 6.4V; Vo = -30dB

V

CC

/2

-1

V

CC

/2

-0.75

V

CC

/2

-0.5

V

VT

ST-BY

St-by Threshold

0.8

1.3

1.8

V

I

ST-BY

St-by Current V6 = GND

100

µ

A

e

N

Total Output Voltage

A Curve

150

µ

V

TDA7266D

4/13

APPLICATIVE SUGGESTIONS

STAND-BY AND MUTE FUNCTIONS

(A) Microprocessor Application

In order to avoid annoying "Pop-Noise" during Turn-On/Off transients, it is necessary to guarantee the right St-
by and mute signals sequence.It is quite simple to obtain this function using a microprocessor (Fig. 1 and 2).

At first St-by signal (from

µ

P) goes high and the voltage across the St-by terminal (Pin 9) starts to increase ex-

ponentially. The external RC network is intended to turn-on slowly the biasing circuits of the amplifier, this to
avoid "POP" and "CLICK" on the outputs.

When this voltage reaches the St-by threshold level, the amplifier is switched-on and the external capacitors in
series to the input terminals (C1, C3) start to charge.

It's necessary to mantain the mute signal low until the capacitors are fully charged, this to avoid that the device
goes in play mode causing a loud "Pop Noise" on the speakers.

A delay of 100-200ms between St-by and mute signals is suitable for a proper operation.

Figure 1. Microprocessor Application

2

5

7

Vref

ST-BY

9

IN1

C1 0.22

µ

F

VCC

15

6

D02AU1409

+

-

-

+

OUT1+

OUT1-

19

16

14

MUTE

8

IN2

C3 0.22

µ

F

+

-

-

+

OUT2+

OUT2-

20

13

S-GND

PW-GND

C5

470

µ

F

C6

100nF

R1 10K

C2

10

µ

F

µ

P

R2 10K

C4

1

µ

F

1

10

11

5/13

TDA7266D

Figure 2. Microprocessor Driving Signals

B) Low Cost Application

In low cost applications where the mP is not present, the suggested circuit is shown in fig.3.

The St-by and mute terminals are tied together and they are connected to the supply line via an external voltage
divider.

The device is switched-on/off from the supply line and the external capacitor C4 is intended to delay the St-by
and mute threshold exceeding, avoiding "Popping" problems.
So to avoid any popping or clicking sond, it is important to clock:

a Correct Sequence: At turn-ON, the Stand-by must be removed at first, then the Mute must be re-

leased after a delay of about 100-200ms. On the contrary at turn-OFF the Mute must be activated
as first and then the Stand-by.
With the values suggested in the Application circuit the right operation is guaranteed.

b Correct Threshold Voltages: In order to avoid that due to the spread in the internal thresholds (see

the above limits) a wrong external voltage causes uncertain commutations for the two functions we
suggest to use the following values:

Mute for Vcc>6.4V

: VT = 2.3V

Mute for Vcc<6.4V

: VT = Vcc/2 - 1

Stand-by

: VT = 0.8V

+V

S

(V)

V

IN

(mV)

V

ST-BY

pin 9

I

q

(mA)

ST-BY

MUTE

PLAY

MUTE

ST-BY

+18

1.8

0.8

V

MUTE

pin 8

4.1

2.3

OFF

OFF

D02AU1411

V

OUT

(V)

2.9

1.3

TDA7266D

6/13

Figure 3. Stand-alone low-cost Application

PCB Layout and External Components:

Regarding the PCB layout care must be taken for three main subjects:

c) Signal and Power Gnd separation

d) Dissipating Copper Area

e) Filter Capacitors positioning

)Signal and Power Gnd separation:

c To the Signal GND must be referred the Audio Input Signals, the Mute and Stand-by Voltages and

the device PIN.13. This Gnd path must be as clean as possible in order to improve the device
THD+Noise and to avoid spurious oscillations across the speakers.
The Power GND is directly connected to the Output power Stage transistors (Emitters) and is crossed
by large amount of current, this path is also used in this device to dissipate the heating generated (no
needs of external heatsinker).
Referring to the typical application circuit, the separation between the two GND paths must be ob-
tained connecting them separately (star routing) to the bulk
Electrolithic capacitor C1 (470

µ

F).

Regarding the Power Gnd dimensioning we have to consider the Dissipated Power the Thermal Pro-
tection Threshold and the Package thermal Characteristics.

2

5

7

Vref

ST-BY

9

IN1

C3 0.22

µ

F

VCC

15

6

D02AU1410

+

-

-

+

OUT1+

OUT1-

19

16

14

MUTE

8

IN2

C5 0.22

µ

F

+

-

-

+

OUT2+

OUT2-

20

13

S-GND

PW-GND

C1

470

µ

F

C2

100nF

C7

100nF

R1

47K

C4

10

µ

F

R2

47K

1

10

11

7/13

TDA7266D

d Dissipating Copper Area:

Dissipated Power:
The max dissipated power happens for a THD near 1% and is given by the formula:

This gives for: Vcc = 9.5V, Rl = 8

Ω

,Iq = 50mA a dissipated power of Pd = 5W.

Thermal Protection:

The thermal protection threshold is placed at a junction temperature of 150°C.

Package Thermal Characteristics:

The thermal resistance Junction to Ambient obtainable with a GND copper Area of 3x3 cm and with 16 via
holes (see picture) is about 15°C/W. This means that with the above mentioned max dissipated Power (Pd=5W)
we can expect a 75°C, this gives a safety margin before the thermal protection intervention in the consumer
environments where a 50°C ambient is specified as maximum

The Thermal constraints determine the max supply voltage that can be used for the different Load Impedances,
this in order to avoid the thermal Protection Intervention.

The max. dissipated power must be not in excess of 5W , this at turns gives the following operating supply volt-
ages:

e Filter Capacitors Positioning:

The two Ceramic capacitors C2/C7 (100nF) must be placed as close as possible
respectively to the two Vcc pins ( 6 - 15) in order to avoid the possibiltiy of oscillations arising on the
output Audio signals.

Package Informations:

You can find a complete description for the PowerSO package into the APPLICATION NOTE AN668 available
on web.

Here we want to focalize the attention only on the the Dissipating elements and ground layer.

Load (Ohm)

Supply Voltage (V)

4

6.5

6

8.5

8

9.5

16

14

P

dm ax W

( )

2

V

C C

2

π

2

Rl

2

------

--------------

I

q

V

CC

+

⋅

=

TDA7266D

8/13

Considering the dissipated power involved in the TDA7266D application that is in the range of 5W, as explained
in a previous section, we suggest via holes ( see fig. 4).

Using via holes a more direct thermal path is obtained from the slug to the ground layer.The number of vias is
chosen accordingly to the desired performance (in our demonstration board we use 15 vias).

In fig.4 is shown as an example the footprint to be used to create the vias.

Figure 4.

The above metioned mounting solution is enough to dissipate the power involved

In the most part of the application using the TDA7266D.

If necessary a further improvement in the Rth J-Ambient can be obtained as shown in fig.5 where the
PowerSO20 is soldered onto a via hole structure with a metal plate glued on the opposite side of the board.

Figure 5. Mounting on epoxy FR4 using via Holes for heat transfer and external metal plate

9/13

TDA7266D

Figure 6. Distortion vs Frequency

Figure 7. Gain vs Frequency

Figure 8. Mute Attenuation vs Vpin.8

Figure 9. Stand-By attenuation vs Vpin 9

Figure 10. Quiescent Current vs Supply Voltage

Figure 11. Total Power Dissipation & Efficiency
vs Pout

0.010

0.1

1

10

100

1k

10k

20k

THD(%)

Vcc = 9.5 V
Rl = 8 ohm

Pout = 100mW

Pout = 2W

frequency (Hz)

-5.000

-4.000

-3.000

-2.000

-1.000

0.0

1.0000

2.0000

3.0000

4.0000

5.0000

10

100

1k

10k

100k

Level(dBr)

Vcc = 9.5V
Rl = 8 ohm
Pout = 1W

frequency (Hz)

1

1.5

2

2.5

3

3.5

4

4.5

5

0

10

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

Attenuation (dB)

Vpin.6(V)

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

2.2

2.4

0

10

-10
-20
-30
-40
-50
-60
-70
-80
-90

-100
-110
-120

Attenuation (dB)

Vpin.7 (V)

3

4

5

6

7

8

9

10

11

12

30

35

40

45

50

55

60

65

70

Iq (mA)

Vsupply(V)

0

1

2

3

4

5

0

1

2

3

4

5

6

10

20

30

40

50

60

70

Pd(W)

Eff(%)

2 X Pout (W)

Vcc= 9.5V

Rl = 8 ohm

f=1KHZ

2 Channels

0

1

2

3

4

5

0

1

2

3

4

5

6

10

20

30

40

50

60

70

Pd(W)

Eff(%)

2 X Pout (W)

Vcc= 9.5V

Rl = 8 ohm

f=1KHZ

2 Channels

TDA7266D

10/13

Figure 12. THD+N vs Output Power

Figure 13. THD+N vs Output Power

10

0.1

0.2

0.5

1

2

5

THD(%)

100m

6

200m 300m 500m700m 1

2

3

4 5

Pout(W)

Vcc=9.5V

Rl=8ohm

f=1KHz

10

0.1

0.2

0.5

1

2

5

THD(%)

100m

6

200m 300m 500m700m 1

2

3

4 5

Pout(W)

Vcc=9.5V

Rl=8ohm

f=1KHz

0.01

10

0.02

0.05

0.1

0.2

0.5

1

2

5

THD(%)

100m

5

200m 300m

500m 700m

1

2

3

4

Pout(W)

Vcc=12V

Rl=16 ohm

f = 1KHz

0.01

10

0.02

0.05

0.1

0.2

0.5

1

2

5

THD(%)

100m

5

200m 300m

500m 700m

1

2

3

4

Pout(W)

Vcc=12V

Rl=16 ohm

f = 1KHz

Figure 14. PC Board Component Layout

11/13

TDA7266D

Figure 15. Evaluation Board Top Layer Layout

Figure 16. Evaluation Board Bottom Layer Layout

TDA7266D

12/13

OUTLINE AND

MECHANICAL DATA

e

a2

A

E

a1

PSO20MEC

DETAIL A

T

D

1

10

11

20

E1

E2

h x 45

DETAIL A

lead

slug

a3

S

Gage Plane

0.35

L

DETAIL B

R

DETAIL B

(COPLANARITY)

G

C

- C -

SEATING PLANE

e3

b

c

N

N

H

BOTTOM VIEW

E3

D1

DIM.

mm

inch

MIN.

TYP.

MAX.

MIN.

TYP.

MAX.

A

3.6

0.142

a1

0.1

0.3

0.004

0.012

a2

3.3

0.130

a3

0

0.1

0.000

0.004

b

0.4

0.53

0.016

0.021

c

0.23

0.32

0.009

0.013

D (1)

15.8

16

0.622

0.630

D1

9.4

9.8

0.370

0.386

E

13.9

14.5

0.547

0.570

e

1.27

0.050

e3

11.43

0.450

E1 (1)

10.9

11.1

0.429

0.437

E2

2.9

0.114

E3

5.8

6.2

0.228

0.244

G

0

0.1

0.000

0.004

H

15.5

15.9

0.610

0.626

h

1.1

0.043

L

0.8

1.1

0.031

0.043

N

8˚ (typ.)

S

8˚ (max.)

T

10

0.394

(1) “D and E1” do not include mold flash or protusions.
- Mold flash or protusions shall not exceed 0.15mm (0.006”)
- Critical dimensions: “E”, “G” and “a3”.

PowerSO20

0056635

JEDEC MO-166

Weight:

1.9gr

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

©

2003 STMicroelectronics - All Rights Reserved

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13/13

TDA7266D