Pamięć ROM (Read-Only Memory)
tylko odczyt, brak wpływu napięcia zasilania Vcc na zawartość pamięci
ROM - programowane przez producenta pamięci w czasie produkcji (MROM -
Podstawy techniki
Mask programmable ROM)
mikroprocesorowej
PROM (Programmable ROM) - pamięć 1-krotnego zapisu (programowania);
programowane przez przepalenie połączeń struktury wewnętrznej
ETEW006
EPROM (Electrically Programmable ROM) - pamięć, programowalna
elektrycznie, kasowana innymi metodami np. przez naświetlanie światłem
ultrafioletowym o wysokiej energii
Pamięci
OTP EPROM (One -Time Programmable EPROM) - pamięć EPROM
1-krotnie programowalna (brak okienka)
ROM i RAM
EEPROM (Erasable Electrically Programmable ROM) - pamięć
wielokrotnego zapisu, kasowalna i programowalna elektrycznie
Flash EEPROM  zapis / kasowanie wielu (bloków) komórek pamięci
Andrzej Stępień podczas jednej operacji programowania
Katedra Metrologii Elektronicznej i Fotonicznej
FRAM (Ferroelectric RAM)  ferroelektryczna pamięć RAM
Types of RAM Memory
Pamięć ulotna RAM
SRAM (Static Random Access Memory) uses multiple transistors, typically
4 to 6, for each memory cell but doesn't have a capacitor in each cell
Pamięć ulotna RAM (Volatile Random Access Memory):
DRAM (Dynamic Random Access Memory ) has memory cells with
a paired transistor and capacitor requiring constant refreshing
pamięć o dostępie swobodnym, utrata zawartości w momencie
zaniku napięcia zasilania Vcc
FPM DRAM (Fast Page Mode Dynamic Random Access Memory)
EDO DRAM (Extended Data-Out Dynamic Random Access Memory)
SRAM (Static RAM):
" przerzutnik bistabilny jako element pamięciowy SDRAM (Synchronous Dynamic Random Access Memory)
" brak cykli odświeżania
DDR SDRAM (Double Data Rate Synchronous Dynamic RAM)
" większa (~4 razy) powierzchnia od pamięci DRAM o tej samej
RDRAM (Rambus Dynamic Random Access Memory)
pojemności
" szybsza w stosunku do pamięci dynamicznej
RIMM (Rambus in-line memory module)
Credit Card Memory, CMOS RAM
DRAM (Dynamic RAM)
" kondensator jako element pamięciowy VRAM (VideoRAM,
known as MPDRAM - Multiport Dynamic Random Access Memory)
" odświeżanie (refresh) ładunku (upływność) kondensatora
" małe rozmiary
SGRAM (Synchronous Graphics RAM)
Samsung Fusion Memory. The Next-Generation Technology for High-Performance
Mobile Applications. Samsung Semiconductor, December 2007
Pamięć nieulotna NVRAM Fusion Memory
As consumers continue their insatiable demand for higher-performance,
Pamięć nieulotna NVRAM (Non-Volatile Random Access Memory)
ever-smaller mobile devices, Samsung s fusion memory products are
increasingly chosen by handheld designers.
pamięć o dostępie swobodnym, zachowanie zawartości w momencie
zaniku napięcia zasilania Vcc
These fusion semiconductors integrate different memory technologies
" pamięci ferrytowe używane w latach 50. i 60. XX wieku and can also include logic, software and other elements on a single
chip. Samsung s fusion products simplify device architecture, reduce power
" pamięci z podtrzymaniem bateryjnym
consumption, increase performance and cut costs while enabling mobile
" NRAM - technologia nanorurek węglowych products to be smaller and deliver greater functionality than ever.
" MRAM  magnetyczny efekt tunelowy magnetycznego
Samsung as the world memory leader and a strong player in mobile logic
" OUM - zmiany stanu stopów pierwiastków rudotwórczych chips, Samsung has exploited its considerable expertise in technologies and
(analogia do płyt CD, DVD  zapis/kasowanie za pomocą lasera, processes to create its fusion memory offerings. These chips are optimal for
zmiana stanu z krystalicznego na amorficzny) today s fast-selling consumer products, from mobile phones, portable
media players and digital cameras to personal navigation devices and
" FRAM - właściwości ferromagnetyczne
multi-function handhelds.
1
Samsung Fusion Memory. The Next-Generation Technology for High-Performance
Mobile Applications. Samsung Semiconductor, December 2007
OneNAND Flash
Memory Parameter (www.st.com Memories)



(NAND core + NOR interface logic + SRAM buffer)
Memory Size  [Storage Capacity] The amount of data that can be contained in a
storage device measured in binary characters, bytes, words, or other units of
data. IEEE Std. 610.10-1994.
Supply Voltage(VCC) - the value as specified by level (minTypMax) of the direct
supply voltage, applied to an IC. IEC61360-AAE690 (VCC).
Memory Organization - Shown as a text representation of the Memory
Organization (i.e. 512 x 8).
Access Time (tACC) - time of address to output delay.
Chip Enable To Output Delay (tCE) - time of chip enable to output delay.
Output Enable To Output Delay(tOE) - time of output enable to output delay.
" The highest-performance flash on the market
Programming Voltage (VPP) / Current (IPP) - Programming voltage or current by
" Included in dozens of different mobile products
the specified test condition
" Has program/erase performance of NAND with NOR s read performance Standby Supply Voltage Current CMOS(ICC2)-Operating supply current by the
specified test condition.
" Can improve booting speed of mobile phones by as much as 20 percent
Operating Temperature - The value as specified by level (minTypMax) of the
" uses up to 60 percent less energy than competing NOR memory ambient temperature (in Cel) in which this item was designed to operate.
Memory
Microprocessor & Memory
&
&
&
Signal Names
Single CS#
VCC  Supply Voltage
Address
VSS  Ground
Decoder Addr
VPP  Program Supply
Data
ROM
A0 .. AXX (Addr)  Address Inputs
Memory
D0 .. DXX or Q0 .. QXX (Data)  Data Inputs / Outputs Addr Address Bus
OE
RD  Data Read
CS
Data Data Bus
WR  Data Write Microprocessor
Microcontroller
Addr
CS or E  Chip Select / Enable
OE or G  Output Enable Data
RD RAM
P  Program
WE Memory
WR
OE
NC  Not Connected Internally
CS
DU  Don t Use
MODE CE OE WE Ai I/O
Address Valid
Standby/Write Inhibit H X X X High Z
Memory
Output disable X H X High Z Memory
Read L L H Ai DOUT
Select Read Waveforms
Program L H L Ai DIN
Single CS# Single CS#
AT29LV512 . 512K (64Kx8) AT29LV512 . 512K (64Kx8)
Address Address Access Time
3-volt Only Flash Memory. 3-volt Only Flash Memory.
tACC Addr
Atmel, 0177O FLASH 9/08 Atmel, 0177O FLASH 9/08
Decoder Addr Decoder
Output
Data Data
Microprocessor Valid
Memory Memory
Microcontroller
Addr Address Bus Addr Address Bus
OE OE
Microprocessor
CS CS
Microcontroller
Data Data Bus Data Data Bus
AC Read Characteristics AT29LV512-12
Addr (A15..0) Addr (A15..0)
Symbol Parameter Units
Data (IO7..0) Data (IO7..0)
tACC Address to Output Delay .. 120 ns
RD
RD
tCE CE to Output Delay .. 120 ns
WE WE
WR
WR Flash tOE OE to Output Delay 0 .. 50 ns Flash
tDF CE or OE to Output Float 0 .. 30 ns
OE Memory OE Memory
ISB1 VCC Standby Current < 50 µA tOH Output Hold from OE, CE 0 .. ns
CS CS
ICC VCC Active Current < 15 mA or Address, whichever occurred first
2
FFFFh= 1111 1111 1111 1111b
F000h = 1111 0000 0000 0000b
Memory Address Memory Address
EFFFh= 1110 1111 1111 1111b
Decoder (1/2) Decoder (2/2) E000h= 1110 0000 0000 0000b
A15 A11 .. 0
FFFFh FFFFh
RAM (8) RAM (8)
9FFFh= 1001 1111 1111 1111b
F000h F000h
EFFFh EFFFh
9000h = 1001 0000 0000 0000b
RAM (7) RAM (7)
E000h E000h
Addr11..0
......... DFFFh ......... DFFFh 8FFFh= 1000 1111 1111 1111b
A15 = 1 A15 = 1
8000h = 1000 0000 0000 0000b
Data7..0 ROM
9FFFh 9FFFh
RAM (2) RAM (2)
16
9000h 9000h 7FFFh= 0111 1111 1111 1111b
A15
Memory
8FFFh 8FFFh
7000h = 0111 0000 0000 0000b
RAM (1) Addr Address Bus 4Kx8 RAM (1)
OE
8000h 8000h
Microprocessor
7FFFh 7FFFh
6FFFh= 0110 1111 1111 1111b
ROM (8) CS ROM (8)
Microcontroller 7000h
7000h
6000h = 0110 0000 0000 0000b
6FFFh 6FFFh
Data Data Bus
ROM (7) ROM (7) A15 A11 .. 0
6000h 6000h
......... 5FFFh 8 Addr11..0 5FFFh
......... 2FFFh= 0010 1111 1111 1111b
A15 = 0 A15 = 0
2000h = 0010 0000 0000 0000b
2FFFh Data7..0 2FFFh
ROM (3) RD RAM ROM (3)
2000h 2000h
1FFFh= 0001 1111 1111 1111b
1FFFh WE Memory 1FFFh
WR
1000h = 0001 0000 0000 0000b
ROM (2) ROM (2)
1000h 1000h
4Kx8
OE
0FFFh 0FFFh
0FFFh= 0000 1111 1111 1111b
ROM (1) ROM (1)
0000h 0000h
CS
0000h = 0000 0000 0000 0000b
TNAL9803. BENEFIT OF DUAL CS. TECHNICAL NOTE
SAMSUNG Electronics CO., LTD. 1998
Dual CS
Single CS SRAM & dual CS SRAM
SRAM
Addr
Data
if system has more than one SRAM or controller can
not drive CS to high at power down mode, you
OE
need additional component on PCB for Data
SRAM
Retention mode WE
If system has more than one SRAM or controller can not drive CS
to high at power down mode, you need additional component on
CS
PCB for Data Retention mode
Addr
if you take dual CS products, you can reduce
Data
if you take dual CS products, you can reduce board area because
board area because you do not need
you do not need additional component
additional component
OE
SRAM
Dual CS products represent frexibility of system design, which
WE
dual CS products represent frexibility of system adopt battery backup mode
design, which adopt battery backup mode
CS1
CS2
M27C64A. 64 Kbit (8Kbit x 8) UV EPROM and OTP EPROM.
STMicroelectronics, October 2002
EPROM
EPROM / OTP EPROM
Parameters
EPROM (Electrically Programmable Read Only Memory) is a nonvolatile
memory which offers the ability to both program and erase the contents Mode E G P VPP Q Output
of the memory multiple times.
Read VIL VIL VIH VCC Data Out
An EPROM must be programmed using a 12.5 volt (or higher) PROM Output Disable VIL VIH VIH VCC Hi-Z
programmer, and then transferred into the system in which it is intended
Program VIL X VIL Pulse VPP Data Input
to function.
Verify VIL VIL VIH VPP Data Output
EPROMs can be erased by shining ultraviolet light into the window in
Standby VIH X X VCC Hi-Z
the top of the IC package. The process of writing data into an EPROM
and then erasing it may be repeated almost indefinitely. EPROMs are
CIN Input Capacitance VIN = 0V 6 pFMAX
usually used for product development, and later replaced with less
COUT Output Capacitance VOUT = 0V 12 pFMAX
expensive one time programmable EPROMs.
OTP EPROM: One Time Programmable EPROM. An EPROM which ICC Supply Current E = VIL G = VIL 30 mAMAX
can only be written with code/data once instead of multiple times. ICC1 Supply Current (Standby) TTL E = VIH G = X 1 mAMAX
Generally, OTP EPROMs are less expensive then erasable EPROMs. ICC2 Supply Current (Standby) CMOS E > VCC  0.2V 100 µAMAX
3
A0-Q12
tAVQV
EPROM
EPROM E
Erasure Operation
Timing
G
erasure begins when the cells are exposed to light with wavelengths shorter
tELQV
than approximately 4000 Å; it should be noted that sunlight and some type of
Q0-Q7
When deliveredhave wavelengths in the 3000-4000 Å range
(and after each erasure for UV EPROM), all bits of the
fluorescent lamps
M27C64A are in the "1 state.
research shows that constant exposure to room level fluorescent lighting
Data is introduced by selectively programming "0"s into the desired bit
could erase a typical M27C64A in about 3 years, while it would take "0"s can
locations. Although only "0"s will be programmed, both "1"s and
approximately 1 weekdata word.
to cause erasure when exposed to direct sunlight
be present in the
tAVQV 250 300
The only way to change a "0" to a "1" is by die exposition to ultraviolet
recommended erasure procedure for the M27C64A is exposure to short
tELQV 250 300
light (UV EPROM). The M27C64A is in the programming mode when
wave ultraviolet light which has a wavelength of 2537 Å
VPP input is at 12.5V, E is at VIL and P is pulsed to VIL.
integrated dose (i.e. UV intensity x exposure time) forparallel to the data
erasure should be a
The data to be programmed is applied to 8 bits in
minimum of 15 W-sec/cm2; erasure time with this dosage is approximately
output pins. The levels required for the address and data inputs are TTL.
15 to 20 minutes using an ultraviolet with 12000 µW/cm2 power rating -
VCC is specified to be 6V Ä… 0.25V.lamp
M27C64A should be placed within 2.5 cm (1 inch) of the lamp tubes during
the erasure
AT25128/AT25256. SPI Serial Automotive EEPROMs 128K (16,384 x 8) / 256K (32,768 x 8)
Atmel Corporation 2002, Rev. 3262A SEEPR 02/02
EEPROM - Flash Memory EEPROM
Serial Peripheral Interface (SPI) Compatible
Medium-voltage and Standard-voltage Operation
 5.0 (VCC = 4.5V to 5.5V)
 2.7 (VCC = 2.7V to 5.5V)
EEPROM:
3 MHz Clock Rate
" erase the entire device all at once
64-byte Page Mode and Byte Write Operation
" program or write single bytes at a time
Block Write Protection  Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for both Hardware and
Software Data Protection
Flash is a high-speed EEPROM:
Self-timed Write Cycle (5 ms Typical)
" program and erase BLOCKS of data at a time
High-reliability
 Endurance: 100,000 Write Cycles
 Data Retention: >200 Years
http://electronics.howstuffworks.com/flash-memory.htm http://electronics.howstuffworks.com/flash-memory.htm
EEPROM EEPROM
(Electronically Erasable Programmable Read Only Memory) Tunneling
charge causes the © HOW STUFF WORKS
©
©
©
EEPROM has a grid
Word Line Word Line
floating-gate transistor to
of columns and rows
act like an electron gun
with a cell that has
Control Control
two transistors at
Gate excited electrons are Gate
Thin Oxide Thin Oxide
Thin Oxide Thin Oxide
each intersection
Layer Layer
Layer Layer
pushed through and
Floating Floating
Gate Gate
trapped on other side of
transistors are sepa-
the thin oxide layer, giving
rated from each other
Drain Source Drain Source
it a negative charge
by a thin oxide layer
Current flow Current flow
these negatively
transistors is known
Negatively charged Negatively charged
as a Floating Gate and Control Gate electrons charged electrons act as electrons
a barrier between the control gate called a cell sensor monitors the level of
as long as this link is in place, the cell has a value of 1  to change the value
the charge passing through the floating gate
to a 0 requires a curious process called Fowler-Nordheim tunneling
if the flow through the gate is above the 50 percent threshold, it has a value
tunneling (and erasing) is used to alter the placement of electrons in the
of 1  when the charge passing through drops below the 50-percent
floating gate (an electrical charge, usually 10 to 13 volts, is applied to the
threshold, the value changes to 0
floating gate)  the charge comes from the column, or bitline, enters the
floating gate and drains to a ground blank EEPROM has all of the gates fully open, giving each cell a value of 1
4
Bit Line
Bit Line
Jim Cooke: ESC-225 NAND 101. An Introduction to NAND Flash and How to Design
it into Your Next Product. Micron Technology, Inc. April 4 2006
Programming Erasing Read
unit: µs/Byte unit: µs/Byte unit: µs/Byte
µ µ µ
µ µ µ
µ µ µ
NOR
15,2
69
NAND / NOR Comparison vs
6,0
NAND
45
44
NAND NOR
" Advantages:
" Advantages:
 Fast writes 0,4
 Random access
0,12
 Fast erases
NAND NAND
 Byte writes possible
NAND NOR NAND NOR NOR
" Disadvantages:
x8 x16
 Slow random access
" Disadvantages:
 Byte writes difficult NAND NOR
 Slow writes
" Applications:
Capacity 1 Gbit x chip 128 Mbit per chip
 File (disk) applications  Slow erase
Power Supply 2,7  3,6 V 2,3  3,6 V
 Voice, data, video recorder
Access Time 50 ns (serial access cycle) 70 ns (30pF; 2,3V)
" Applications
 Any large sequential data
25 µs (random access) 65 ns (30pF, 2,7V)
µ
µ
µ
 Replacement of EPROM
Programm Speed (typ) 200 µ µ
µs / 512 Byte 8 µs / Byte
µ µ
µ µ
 Execute directly from Erase Speed (typ) 2 ms / Block (16 KB) 4,1 ms / 512 Byte
Figure 4: NAND/NOR comparison
nonvolatile memory
Prog + Erase (typ) 33,6 ms / 64 KB 700 ms / Block
SRAM (Static Random Access Memory) NV SRAM (NonVolatile Static Random Access Memory)
NV SRAM is a single package which contains a low power SRAM, a
nonvolatile memory controller, and a lithium type battery
is essentially a stable DC flip flop requiring no clock timing or
refreshing
when the power supply to this single modular package falls below the
minimum requirement to maintain the contents of the SRAM, the memory
controller in the module switches the power supply from the external
contents of an SRAM memory are retained as long as power is
source to the internal lithium battery and write protects the SRAM
supplied
these transitions to and from the external power source are transparent to
the SRAM, making it a true nonvolatile memory
SRAMs support extremely fast access times
this unique construction combines the strategic advantages of SRAM
addressing structure, high speed access, and timing requirements  with the
nonvolatility advantages of EEPROM technologies
SRAMs also have relatively few strict timing requirements and a
parallel address structure, making them particularly suited for
Battery backed SRAM modules from Dallas Semiconductor are pin
cache and other low density, frequent access applications
compatible with non battery backed SRAMs, making them ideal for any
application where a traditional SRAM would be suitable
SRAM
SRAM
Single Access Read Cycle K6R1008V1D (1/3)
K6R1008V1D.
tRC Read Cycle Time
1Mbit Asynchronous Fast SRAM
High-Speed CMOS Static RAM.
tAA Address Access Time
Samsung Electronics June 2003
tOH Output Hold from Address Change
A0 - A16 Address Inputs
tRC
CS WE OE Mode I/O Pin Supply Current
WE Write Enable
H X X* Not Select High-Z ISB, ISB1
CS Chip Select
Address
L H H Output Disable High-Z ICC
OE Output Enable
tAA L I/O1 ~ I/O8 Data Inputs/Outputs ICC
H L Read DOUT
VCC Power(+3.3V)
L L X Write DIN ICC
tOH
VSS Ground
Data Out Previous Data Valid ??? Data Valid
5
K6R1008V1D. 1Mbit Asynchronous Fast SRAM High-Speed CMOS Static RAM. K6R1008V1D. 1Mbit Asynchronous Fast SRAM High-Speed CMOS Static RAM.
Samsung Electronics June 2003 Samsung Electronics June 2003
SRAM - READ K6R1008V1D-08 (2/3) SRAM - Write K6R1008V1D-08 (3/3)
(OE= Clock)
Read Cycle Time tRC 8 nsMIN
Address Access Time tAA 8 nsMAX
Write Cycle Time tWC 8 nsMIN (OE=Low Fixed)
Chip Select to Output tCO 8 nsMAX
Chip Select to End of Write tCW 6 nsMIN (CS = Controlled)
Output Enable to Valid Output tOE 4 nsMAX
Address Set-up Time tAS 0 nsMIN
Output Hold from Address Change tOH 3 nsMIN
Address Valid to End of Write tAW 6 nsMIN
Write Pulse Width(OE High) tWP 6 nsMIN
Chip Selection to Power Up Time tPU 0 nsMIN
Chip Selection to Power DownTime tPD 8 nsMAX End of Write to Output Low-Z tOW 3 nsMIN
Memory & Memory Memory & Memory
& &
& &
& &
Dynamic Static
K6R1008V1D. 1Mbit Asynchronous Fast SRAM High-Speed CMOS Static RAM.
K6R1008V1D. 1Mbit Asynchronous Fast SRAM High-Speed CMOS Static RAM.
Samsung Electronics June 2003
Samsung Electronics June 2003
K6F1008V2C. 128Kx8 bit Super Low Power and Low Voltage CMOS Static RAM.
K6F1008V2C. 128Kx8 bit Super Low Power and Low Voltage CMOS Static RAM.
Samsung Electronics, March 2005
Samsung Electronics, March 2005
K6R1008V1D-08 K6F1008V2C-55
Parameter Symbol K6R1008V1D-08 K6F1008V2C-55
Read Cycle Time tRC 8 nsMIN 55 nsMIN
Address Access Time tAA 8 nsMAX 55 nsMAX
Operating ICC2 90 mA 35 mAMAX TTL
CS=0
Chip Select to Output tCO 8 nsMAX 55 nsMAX
Current ICC1 3 mAMAX CMOS
Output Enable to Valid Output tOE 4 nsMAX 25 nsMAX
Output Hold from Address Change tOH 3 nsMIN 10 nsMIN Standby ISB 20 mA TTL
CS=1
Current ISB1 5 mA 5 µAMAX CMOS
Write Cycle Time tWC 8 nsMIN 55 nsMIN
Chip Select to End of Write tCW 6 nsMIN 45 nsMIN
Input/Output Capacitance
Address Set-up Time tAS 0 nsMIN 0 nsMIN
CI/O 8 pFMAX 10 pFMAX
Address Valid to End of Write tAW 6 nsMIN 45 nsMIN
Input Capacitance
Write Pulse Width(OE High) tWP 6 nsMIN 40 nsMIN
CIN 6 pFMAX 8 pFMAX
End of Write to Output Low-Z tOW 3 nsMIN 5 nsMIN
DRAM (Dynamic Random Access Memory) SRAM / DRAM Cell
in an SRAM, this information is stored in a four to six transistor flip
SRAM Cell DRAM Cell
flop which is easy to address, but requires a relatively large memory
cell
Switching
Select = 1
element
DRAM, by comparison, stores its 1 or 0 as a charge on a small
capacitor, requir ing much more current then an SRAM to maintain the
Word Line
P1 P2
stored data
Off On Sense
Amplifier
net memory cell size is smaller for the DRAM than for the SRAM, so
On Bit
On
C Storage
the total cost per bit of memory is less Line
On Off
element
(capacitor)
N1 N2
DRAM s capacitors must be constantly refreshed so that they retain
their charge
C = 0,020  0,040 pF
bit = 1 bit = 0
DRAMs require more sophisticated interface circuitry
6
SLOW
FAST
FAST
SLOW
Understanding DRAM Operation.
Applications Note. IBM, December 1996
DRAM
DRAM Architecture
Memory Circuits
Memory Controller include a series of tasks that include identifying the type,
DRAM Cell
Column Decoder speed and amount of memory and checking for errors
Switching
Data In/Out element
memory cells have a whole support infrastructure of other specialized circuits
Sense Amps
Buffers
Word Line to perform functions:
.. Bit Lines ..
 address logic to select rows and columns: RAS (Row Address Select) and
Storage
CAS (Column Address Select)
Bit element
Line (capacitor)
 internal Refresh Counters or registers to keep track of the refresh
Memory
sequence, or to initiate refresh cycles as needed
Array
 Sense Amplifier to amplify the signal or charge detected on a memory
RAS  Row Access Select cell
CAS  Column Access Select
 WE (Write Enable) telling a cell whether it should take a charge or not
R/W  Read / Write
OE  Output Enable  OE (Output Enable) logic to prevent data from appearing at the outputs
Data Addr RAS CAS R/W OE CS
CS  Chip Select unless specifically desired.
Robert Hoffmann: Engineer To Engineer. Note EE-126.
http://computer.howstuffworks.com/ram.htm
European DSP Applications. Analog Devices, Rev1 (20-March-02)
TN-04-30. VARIOUS METHODS OF DRAM REFRESH
DRAM
Micron Technology, Rev. 2/1999
DRAM
Refresh
AN987. DRAM Refresh Modes.
Refresh
Refresh
Motorola Semiconductors. REV 1. February 1994
capacitor is like a small bucket that is
MT4LC4M4E8, MT4LC4M4E9. 4 MEG x 4 EDO DRAM.
able to store electrons
Micron Technology Rev. 6/1998
K4S64xx32N Synchronous DRAM. 2M x 8Bit x 4Banks / 1M x 16Bit x
to store a 1 in the memory cell, the
4Banks SDRAM. Samsung Electronics, Rev. 1.12 August 2008
bucket is filled with electrons
each cell unit consisting of a transistor and a very small capacitor of about
to store a 0, it is emptied 20-40 fF (Femtofarad, 0.020-0.040 pF) - a charged capacitor has a logical 1,
a discharged capacitor a logical 0
problem with the capacitor's bucket is
that it has a leak, in a matter of a few DRAM must refresh the row each time the spec tREF is elapsed
milliseconds a full bucket becomes empty Micron Technology:
refresh period tREF = 32 / 64 ms (2,048 / 4,096 cycles)
CPU or the memory controller has to come along and recharge all of the Samsung Electronics (Auto refresh):
capacitors holding a 1 before they discharge  to do this, the memory refresh period tREF = 64 ms (4K cycles)
controller reads the memory and then writes it right back
3 different refresh modes are available:
refresh operation happens automatically thousands of times per second RAS only Refresh, Hidden Refresh, CAS before RAS Refresh
1. Activation:
 bias the row s bit lines 2. Access Column: 3. Precharge:
 sense the word lines  select bit lines  write stored value back to
DRAM - timing What does 4-3-3 SDRAM mean
capacitor cells  WR: write to sense amp the cell
 store sensed value  RD: read stored value  deselect row and columns
statically tRC
Engineer To Engineer. Note EE-126 Contributed by Robert Hoffmann,
tCLK = 7,5 ns (133 MHz Bus)
tRP = 20 ns
tRAS tRP
4  3  3
European DSP Applications. Analog Devices, Rev1 (20-March-02)
tRAS
CL = tCAC / tCLK = 3,33 4



~RAS
~RAS
CL is CAS Latency

~CAS tRP / tCLK = 2,67 3


~CAS
tRCD
tRCD = 20 ns
tCAS
tCAS
tRCD / tCLK = 2,67 3



~WE tWCS tWCH tCAC
~WE
tCAC = 25 ns
~OE
~OE
Address Row Col Row Col
Address Row Col Row Col
tRAC
tARS tARH tACS tACH
Idle state
Idle state
Data
D Q
Data
D
Q
7
Row Decoder
.. Word Lines ..
FRAM Operation
What does 2-3-3-6-1T DRAM mean
ferroelectric crystal has a mobile atom in the center of the crystal,
applying an electric field across a face of the crystal causes this atom to move
in the direction of the field
tCLK = 7,5 ns (133 MHz Bus)
tRAS = 40 ns tRP = 20 ns
2  3  3  6
reversing the field causes the atom to move in the opposite direction
CL = tCAC / tCLK = 2 2



atom positions at the top and bottom of the crystal are stable
~RAS
CL is CAS Latency
removing the electric field
tRP / tCLK = 2,67 3



leaves the atom in a
~CAS
tRCD = 20 ns
tCAS
stable position, even in the
tRCD / tCLK = 2,67 3



absence of power
~WE tRAS / tCLK = 5,33 6



tCAC = 15 ns
as a memory element, the
Bank cycle time
ferroelectric crystal creates
~OE
an ideal digital memory - it
contains two stable data
Address Row Col Row Col
states, it requires very little
time and energy to change
tRAC
states, and is very stable
Idle state over a variety of
Data
D
Q
environmental conditions
Sun S. Sommervold B. Culbreth T. Davenport T: Data Retention Performance of 0.5 µm AN-200. Advantages of the FM24C16 Serial 16Kb FRAM Memory.
FRAM Products. Technical paper, Ramtron, Apr. 2006 Ramtron, Jan. 1999
Advantages of the FRAM Memory
FRAM
8