Timing report for automat





Timing Report
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Design Name
automat


Device, Speed (SpeedFile Version)
XC2C256, -6 (14.0 Advance Product Specification)


Date Created Mon Mar 11 11:27:08 2013



Created By Timing Report Generator: version P.49d


Copyright Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.


Summary


Notes and Warnings


Note: This design contains no timing constraints.


Note: A default set of constraints using a delay of 0.000ns will be used for analysis.


Possible asynchronous logic: Clock pin 'FB1__ctinst/4' has multiple original clock nets 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q'.




Performance Summary


Min. Clock Period
5.000 ns.


Max. Clock Frequency (fSYSTEM)
200.000 MHz.


Limited by Cycle Time for XLXN_5_MC.Q


Clock to Setup (tCYC)
5.000 ns.


Setup to Clock at the Pad (tSU)
2.600 ns.


Clock Pad to Output Pad Delay (tCO)
11.500 ns.



Timing Constraints


Constraint Name
Requirement (ns)
Delay (ns)
Paths
Paths Failing


TS1000
0.0
0.0
0
0


TS1001
0.0
0.0
0
0


TS1002
0.0
0.0
0
0


TS1003
0.0
0.0
0
0


TS1004
0.0
0.0
0
0


TS1005
0.0
0.0
0
0


TS1006
0.0
0.0
0
0


TS1007
0.0
0.0
0
0


TS1008
0.0
0.0
0
0


TS1009
0.0
0.0
0
0


AUTO_TS_F2F
0.0
5.0
30
30


AUTO_TS_P2P
0.0
11.5
2
2


AUTO_TS_P2F
0.0
5.3
13
13


AUTO_TS_F2P
0.0
2.7
2
2





Constraint: TS1000

Description: PERIOD:PERIOD_CLK:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1001

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1002

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1003

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1004

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1005

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1006

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1007

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1008

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1009

Description: PERIOD:PERIOD_XLXN_5_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



OUT0.Q to OUT1.D
0.000
5.000
-5.000






OUT1.Q to OUT1.D
0.000
5.000
-5.000






XLXI_2/XLXI_14/Q.Q to XLXI_2/XLXI_14/Q.D
0.000
3.900
-3.900








Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



CLK to OUT0
0.000
11.500
-11.500






CLK to OUT1
0.000
11.500
-11.500








Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



IN0 to OUT1.D
0.000
5.300
-5.300






IN1 to OUT1.D
0.000
5.300
-5.300






IN0 to OUT0.D
0.000
5.000
-5.000








Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



OUT0.Q to OUT0
0.000
2.700
-2.700






OUT1.Q to OUT1
0.000
2.700
-2.700







Number of constraints not met: 4


Data Sheet Report

Maximum External Clock Speeds


Clock
fEXT (MHz)
Reason


CLK
454.545
Limited by External Clock Pulse Width for CLK


XLXI_2/XLXI_14/Q_MC.Q
454.545
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXI_2/XLXI_14/Q_MC.Q
454.545
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXI_2/XLXI_14/Q_MC.Q
454.545
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXI_2/XLXI_14/Q_MC.Q
454.545
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXI_2/XLXI_14/Q_MC.Q
454.545
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXI_2/XLXI_14/Q_MC.Q
454.545
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXI_2/XLXI_14/Q_MC.Q
454.545
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXI_2/XLXI_14/Q_MC.Q
454.545
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXN_5_MC.Q
200.000
Limited by Cycle Time for XLXN_5_MC.Q




Setup/Hold Times for Clocks

Setup/Hold Times for Clock CLK

Source Pad
Setup to clk (edge)
Hold to clk (edge)


PYK
2.600
0.000



Setup/Hold Times for Clock XLXN_5.Q

Source Pad
Setup to clk (edge)
Hold to clk (edge)


IN0
1.800
0.000


IN1
1.800
0.000




Clock to Pad Timing

Clock CLK to Pad

Destination Pad
Clock (edge) to Pad


OUT0
11.500


OUT1
11.500




Clock to Setup Times for Clocks

Clock to Setup for clock CLK

Source
Destination
Delay


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900



Clock to Setup for clock XLXN_5.Q

Source
Destination
Delay


OUT0.Q
OUT1.D
5.000


OUT1.Q
OUT1.D
5.000




Pad to Pad List


Source Pad
Destination Pad
Delay




Number of paths analyzed:
47
Number of Timing errors:
47
Analysis Completed: Mon Mar 11 11:27:08 2013