Timing report for glowny





Timing Report
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Design Name
glowny


Device, Speed (SpeedFile Version)
XC2C256, -6 (14.0 Advance Product Specification)


Date Created Mon Apr 08 12:11:05 2013



Created By Timing Report Generator: version P.49d


Copyright Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.


Summary


Notes and Warnings


Note: This design contains no timing constraints.


Note: A default set of constraints using a delay of 0.000ns will be used for analysis.


Possible asynchronous logic: Clock pin 'XLXN_13.CLKF' has multiple original clock nets 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q'.




Performance Summary


Min. Clock Period
12.000 ns.


Max. Clock Frequency (fSYSTEM)
83.333 MHz.


Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


Clock to Setup (tCYC)
4.700 ns.


Setup to Clock at the Pad (tSU)
1.500 ns.


Clock Pad to Output Pad Delay (tCO)
11.500 ns.



Timing Constraints


Constraint Name
Requirement (ns)
Delay (ns)
Paths
Paths Failing


TS1000
0.0
0.0
0
0


TS1001
0.0
0.0
0
0


TS1002
0.0
0.0
0
0


TS1003
0.0
0.0
0
0


TS1004
0.0
0.0
0
0


TS1005
0.0
0.0
0
0


TS1006
0.0
0.0
0
0


TS1007
0.0
0.0
0
0


TS1008
0.0
0.0
0
0


TS1009
0.0
0.0
0
0


AUTO_TS_F2F
0.0
4.7
31
31


AUTO_TS_P2P
0.0
11.5
8
8


AUTO_TS_P2F
0.0
5.0
6
6


AUTO_TS_F2P
0.0
2.7
8
8





Constraint: TS1000

Description: PERIOD:PERIOD_p38:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1001

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1002

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1003

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1004

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1005

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1006

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1007

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1008

Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: TS1009

Description: PERIOD:PERIOD_XLXN_13_MC.Q:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



out4.Q to out5.D
0.000
4.700
-4.700






out5.Q to out6.D
0.000
4.700
-4.700






out6.Q to out7.D
0.000
4.700
-4.700








Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



p38 to out0
0.000
11.500
-11.500






p38 to out1
0.000
11.500
-11.500






p38 to out2
0.000
11.500
-11.500








Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



in0 to out0.D
0.000
5.000
-5.000






in0 to out4.D
0.000
5.000
-5.000






in1 to out2.D
0.000
5.000
-5.000








Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



out0.Q to out0
0.000
2.700
-2.700






out1.Q to out1
0.000
2.700
-2.700






out2.Q to out2
0.000
2.700
-2.700







Number of constraints not met: 4


Data Sheet Report

Maximum External Clock Speeds


Clock
fEXT (MHz)
Reason


p38
454.545
Limited by External Clock Pulse Width for p38


XLXI_2/XLXI_14/Q_MC.Q
83.333
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXI_2/XLXI_14/Q_MC.Q
83.333
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXI_2/XLXI_14/Q_MC.Q
83.333
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXI_2/XLXI_14/Q_MC.Q
83.333
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXI_2/XLXI_14/Q_MC.Q
83.333
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXI_2/XLXI_14/Q_MC.Q
83.333
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXI_2/XLXI_14/Q_MC.Q
83.333
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXI_2/XLXI_14/Q_MC.Q
83.333
Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q


XLXN_13_MC.Q
212.766
Limited by Cycle Time for XLXN_13_MC.Q




Setup/Hold Times for Clocks

Setup/Hold Times for Clock XLXN_13.Q

Source Pad
Setup to clk (edge)
Hold to clk (edge)


in0
1.500
0.000


in1
1.500
0.000


in2
1.500
0.000


in3
1.500
0.000




Clock to Pad Timing

Clock p38 to Pad

Destination Pad
Clock (edge) to Pad


out0
11.500


out1
11.500


out2
11.500


out3
11.500


out4
11.500


out5
11.500


out6
11.500


out7
11.500




Clock to Setup Times for Clocks

Clock to Setup for clock p38

Source
Destination
Delay


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900


XLXI_2/XLXI_14/Q.Q
XLXI_2/XLXI_14/Q.D
3.900



Clock to Setup for clock XLXN_13.Q

Source
Destination
Delay


out4.Q
out5.D
4.700


out5.Q
out6.D
4.700


out6.Q
out7.D
4.700




Pad to Pad List


Source Pad
Destination Pad
Delay




Number of paths analyzed:
53
Number of Timing errors:
53
Analysis Completed: Mon Apr 08 12:11:05 2013