Timing report for top





Timing Report
Need help reading this report?


Design Name
top


Device, Speed (SpeedFile Version)
XC2C256, -6 (14.0 Advance Product Specification)


Date Created Mon May 27 11:55:36 2013



Created By Timing Report Generator: version P.49d


Copyright Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.


Summary


Notes and Warnings


Note: This design contains no timing constraints.


Note: A default set of constraints using a delay of 0.000ns will be used for analysis.




Performance Summary


Min. Clock Period
4.200 ns.


Max. Clock Frequency (fSYSTEM)
238.095 MHz.


Limited by Cycle Time for zegar_in


Clock to Setup (tCYC)
4.200 ns.


Pad to Pad Delay (tPD)
5.700 ns.


Setup to Clock at the Pad (tSU)
2.700 ns.


Clock Pad to Output Pad Delay (tCO)
7.500 ns.



Timing Constraints


Constraint Name
Requirement (ns)
Delay (ns)
Paths
Paths Failing


TS1000
0.0
0.0
0
0


AUTO_TS_F2F
0.0
4.2
13
13


AUTO_TS_P2P
0.0
7.5
8
8


AUTO_TS_P2F
0.0
4.5
12
12


AUTO_TS_F2P
0.0
5.7
28
28





Constraint: TS1000

Description: PERIOD:PERIOD_zegar_in:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



liczenie.Q to liczenie.D
0.000
4.200
-4.200






liczenie.Q to liczenie.D
0.000
4.200
-4.200






liczenie.Q to liczenie.D
0.000
4.200
-4.200








Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



zegar_in to LED
0.000
7.500
-7.500






zegar_in to LED
0.000
7.500
-7.500






zegar_in to LED
0.000
7.500
-7.500








Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



btn0 to liczenie.D
0.000
4.500
-4.500






btn0 to liczenie.D
0.000
4.500
-4.500






btn0 to liczenie.D
0.000
4.500
-4.500








Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



liczenie.Q to LED
0.000
5.700
-5.700






liczenie.Q to LED
0.000
5.700
-5.700






liczenie.Q to LED
0.000
5.700
-5.700







Number of constraints not met: 4


Data Sheet Report

Maximum External Clock Speeds


Clock
fEXT (MHz)
Reason


zegar_in
238.095
Limited by Cycle Time for zegar_in




Setup/Hold Times for Clocks

Setup/Hold Times for Clock zegar_in

Source Pad
Setup to clk (edge)
Hold to clk (edge)


btn0
2.700
0.000


sw0
2.700
0.000


sw1
2.700
0.000




Clock to Pad Timing

Clock zegar_in to Pad

Destination Pad
Clock (edge) to Pad


LED
7.500


LED
7.500


LED
7.500


LED
7.500


LED
7.500


LED
7.500


LED
7.200




Clock to Setup Times for Clocks

Clock to Setup for clock zegar_in

Source
Destination
Delay


liczenie.Q
liczenie.D
4.200


liczenie.Q
liczenie.D
4.200


liczenie.Q
liczenie.D
4.200


liczenie.Q
liczenie.D
4.200


liczenie.Q
liczenie.D
4.200


liczenie.Q
liczenie.D
4.200


liczenie.Q
liczenie.D
4.200


liczenie.Q
liczenie.D
4.200


liczenie.Q
liczenie.D
4.200


liczenie.Q
liczenie.D
4.200


liczenie.Q
liczenie.D
4.200


liczenie.Q
liczenie.D
4.200


liczenie.Q
liczenie.D
4.200




Pad to Pad List


Source Pad
Destination Pad
Delay


zegar_in
dioda
5.700




Number of paths analyzed:
61
Number of Timing errors:
61
Analysis Completed: Mon May 27 11:55:36 2013