Timing report for licznik6





Timing Report
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Design Name
licznik6


Device, Speed (SpeedFile Version)
XC2C256, -6 (14.0 Advance Product Specification)


Date Created Mon Mar 18 12:39:08 2013



Created By Timing Report Generator: version P.49d


Copyright Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.


Summary


Notes and Warnings


Note: This design contains no timing constraints.


Note: A default set of constraints using a delay of 0.000ns will be used for analysis.




Performance Summary


Min. Clock Period
4.200 ns.


Max. Clock Frequency (fSYSTEM)
238.095 MHz.


Limited by Cycle Time for XLXN_29


Clock to Setup (tCYC)
4.200 ns.


Clock Pad to Output Pad Delay (tCO)
4.500 ns.



Timing Constraints


Constraint Name
Requirement (ns)
Delay (ns)
Paths
Paths Failing


TS1000
0.0
0.0
0
0


AUTO_TS_F2F
0.0
4.2
6
6


AUTO_TS_P2P
0.0
4.5
3
3


AUTO_TS_P2F
0.0
1.8
1
1


AUTO_TS_F2P
0.0
2.7
3
3





Constraint: TS1000

Description: PERIOD:PERIOD_XLXN_29:0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)





Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



q0.Q to q1.D
0.000
4.200
-4.200






q0.Q to q2.D
0.000
4.200
-4.200






q1.Q to q1.D
0.000
4.200
-4.200








Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



XLXN_29 to q0
0.000
4.500
-4.500






XLXN_29 to q1
0.000
4.500
-4.500






XLXN_29 to q2
0.000
4.500
-4.500








Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



XLXN_29 to XLXN_29.GCK
0.000
1.800
-1.800








Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS

Path
Requirement (ns)
Delay (ns)
Slack (ns)



q0.Q to q0
0.000
2.700
-2.700






q1.Q to q1
0.000
2.700
-2.700






q2.Q to q2
0.000
2.700
-2.700







Number of constraints not met: 4


Data Sheet Report

Maximum External Clock Speeds


Clock
fEXT (MHz)
Reason


XLXN_29
238.095
Limited by Cycle Time for XLXN_29




Setup/Hold Times for Clocks


Clock to Pad Timing

Clock XLXN_29 to Pad

Destination Pad
Clock (edge) to Pad


q0
4.500


q1
4.500


q2
4.500




Clock to Setup Times for Clocks

Clock to Setup for clock XLXN_29

Source
Destination
Delay


q0.Q
q1.D
4.200


q0.Q
q2.D
4.200


q1.Q
q1.D
4.200


q1.Q
q2.D
4.200


q2.Q
q1.D
4.200


q2.Q
q2.D
4.200




Pad to Pad List


Source Pad
Destination Pad
Delay




Number of paths analyzed:
13
Number of Timing errors:
13
Analysis Completed: Mon Mar 18 12:39:08 2013