Timing report for glowny Timing Report Need help reading this report? Design Name glowny Device, Speed (SpeedFile Version) XC2C256, -6 (14.0 Advance Product Specification) Date Created Mon Jun 03 11:56:33 2013 Created By Timing Report Generator: version P.49d Copyright Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Summary Notes and Warnings Note: This design contains no timing constraints. Note: A default set of constraints using a delay of 0.000ns will be used for analysis. Possible asynchronous logic: Clock pin 'FB1__ctinst/4' has multiple original clock nets 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q' 'XLXI_2/XLXI_14/Q_MC.Q'. Performance Summary Min. Clock Period 2.200 ns. Max. Clock Frequency (fSYSTEM) 454.545 MHz. Limited by External Clock Pulse Width for CLK Clock to Setup (tCYC) 3.900 ns. Clock Pad to Output Pad Delay (tCO) 11.500 ns. Timing Constraints Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing TS1000 0.0 0.0 0 0 TS1001 0.0 0.0 0 0 TS1002 0.0 0.0 0 0 TS1003 0.0 0.0 0 0 TS1004 0.0 0.0 0 0 TS1005 0.0 0.0 0 0 TS1006 0.0 0.0 0 0 TS1007 0.0 0.0 0 0 TS1008 0.0 0.0 0 0 TS1009 0.0 0.0 0 0 AUTO_TS_F2F 0.0 3.9 28 28 AUTO_TS_P2P 0.0 11.5 2 2 AUTO_TS_P2F 0.0 1.8 1 1 AUTO_TS_F2P 0.0 2.7 2 2 Constraint: TS1000 Description: PERIOD:PERIOD_CLK:0.000 nS Path Requirement (ns) Delay (ns) Slack (ns) Constraint: TS1001 Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS Path Requirement (ns) Delay (ns) Slack (ns) Constraint: TS1002 Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS Path Requirement (ns) Delay (ns) Slack (ns) Constraint: TS1003 Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS Path Requirement (ns) Delay (ns) Slack (ns) Constraint: TS1004 Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS Path Requirement (ns) Delay (ns) Slack (ns) Constraint: TS1005 Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS Path Requirement (ns) Delay (ns) Slack (ns) Constraint: TS1006 Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS Path Requirement (ns) Delay (ns) Slack (ns) Constraint: TS1007 Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS Path Requirement (ns) Delay (ns) Slack (ns) Constraint: TS1008 Description: PERIOD:PERIOD_XLXI_2/XLXI_14/Q_MC.Q:0.000 nS Path Requirement (ns) Delay (ns) Slack (ns) Constraint: TS1009 Description: PERIOD:PERIOD_XLXN_2_MC.Q:0.000 nS Path Requirement (ns) Delay (ns) Slack (ns) Constraint: AUTO_TS_F2F Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS Path Requirement (ns) Delay (ns) Slack (ns) XLXI_2/XLXI_14/Q.Q to XLXI_2/XLXI_14/Q.D 0.000 3.900 -3.900 XLXI_2/XLXI_14/Q.Q to XLXI_2/XLXI_14/Q.D 0.000 3.900 -3.900 XLXI_2/XLXI_14/Q.Q to XLXI_2/XLXI_14/Q.D 0.000 3.900 -3.900 Constraint: AUTO_TS_P2P Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS Path Requirement (ns) Delay (ns) Slack (ns) CLK to Y1 0.000 11.500 -11.500 CLK to Y2 0.000 11.500 -11.500 Constraint: AUTO_TS_P2F Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS Path Requirement (ns) Delay (ns) Slack (ns) CLK to CLK.GCK 0.000 1.800 -1.800 Constraint: AUTO_TS_F2P Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS Path Requirement (ns) Delay (ns) Slack (ns) Y1.Q to Y1 0.000 2.700 -2.700 Y2.Q to Y2 0.000 2.700 -2.700 Number of constraints not met: 4 Data Sheet Report Maximum External Clock Speeds Clock fEXT (MHz) Reason CLK 454.545 Limited by External Clock Pulse Width for CLK XLXI_2/XLXI_14/Q_MC.Q 454.545 Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q XLXI_2/XLXI_14/Q_MC.Q 454.545 Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q XLXI_2/XLXI_14/Q_MC.Q 454.545 Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q XLXI_2/XLXI_14/Q_MC.Q 454.545 Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q XLXI_2/XLXI_14/Q_MC.Q 454.545 Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q XLXI_2/XLXI_14/Q_MC.Q 454.545 Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q XLXI_2/XLXI_14/Q_MC.Q 454.545 Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q XLXI_2/XLXI_14/Q_MC.Q 454.545 Limited by Clock Pulse Width for XLXI_2/XLXI_14/Q_MC.Q XLXN_2_MC.Q 454.545 Limited by Clock Pulse Width for XLXN_2_MC.Q Setup/Hold Times for Clocks Clock to Pad Timing Clock CLK to Pad Destination Pad Clock (edge) to Pad Y1 11.500 Y2 11.500 Clock to Setup Times for Clocks Clock to Setup for clock CLK Source Destination Delay XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 XLXI_2/XLXI_14/Q.Q XLXI_2/XLXI_14/Q.D 3.900 Pad to Pad List Source Pad Destination Pad Delay Number of paths analyzed: 33 Number of Timing errors: 33 Analysis Completed: Mon Jun 03 11:56:33 2013